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llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
| Show First 20 Lines • Show All 1136 Lines • ▼ Show 20 Line(s) | 1135 | def : GCNPat < | |||
|---|---|---|---|---|---|
| 1137 | (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) | 1137 | (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) | ||
| 1138 | >; | 1138 | >; | ||
| 1139 | 1139 | | |||
| 1140 | def : GCNPat < | 1140 | def : GCNPat < | ||
| 1141 | (i32 imm:$imm), | 1141 | (i32 imm:$imm), | ||
| 1142 | (S_MOV_B32 imm:$imm) | 1142 | (S_MOV_B32 imm:$imm) | ||
| 1143 | >; | 1143 | >; | ||
| 1144 | 1144 | | |||
| 1145 | def : GCNPat < | ||||
| 1146 | (VGPRImm<(SIlds tglobaladdr:$ga)>), | ||||
| 1147 | (V_MOV_B32_e32 $ga) | ||||
| 1148 | >; | ||||
| 1149 | | ||||
| 1150 | def : GCNPat < | ||||
| 1151 | (SIlds tglobaladdr:$ga), | ||||
| 1152 | (S_MOV_B32 $ga) | ||||
| 1153 | >; | ||||
| 1154 | | ||||
| 1145 | // FIXME: Workaround for ordering issue with peephole optimizer where | 1155 | // FIXME: Workaround for ordering issue with peephole optimizer where | ||
| 1146 | // a register class copy interferes with immediate folding. Should | 1156 | // a register class copy interferes with immediate folding. Should | ||
| 1147 | // use s_mov_b32, which can be shrunk to s_movk_i32 | 1157 | // use s_mov_b32, which can be shrunk to s_movk_i32 | ||
| 1148 | def : GCNPat < | 1158 | def : GCNPat < | ||
| 1149 | (VGPRImm<(f16 fpimm)>:$imm), | 1159 | (VGPRImm<(f16 fpimm)>:$imm), | ||
| 1150 | (V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm))) | 1160 | (V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm))) | ||
| 1151 | >; | 1161 | >; | ||
| 1152 | 1162 | | |||
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