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llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
| ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s | ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s | ||||
| ; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s | ; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s | ||||
| ; Test that SIMachineFunctionInfo can be round trip serialized through | ; Test that SIMachineFunctionInfo can be round trip serialized through | ||||
| ; MIR. | ; MIR. | ||||
| @lds = addrspace(3) global [512 x float] undef, align 4 | @lds = addrspace(3) global [512 x float] undef, align 4 | ||||
| ; CHECK-LABEL: {{^}}name: kernel | ; CHECK-LABEL: {{^}}name: kernel | ||||
| ; CHECK: machineFunctionInfo: | ; CHECK: machineFunctionInfo: | ||||
| ; CHECK-NEXT: explicitKernArgSize: 128 | ; CHECK-NEXT: explicitKernArgSize: 128 | ||||
| ; CHECK-NEXT: maxKernArgAlign: 64 | ; CHECK-NEXT: maxKernArgAlign: 64 | ||||
| ; CHECK-NEXT: ldsSize: 2048 | ; CHECK-NEXT: ldsSize: 0 | ||||
| ; CHECK-NEXT: isEntryFunction: true | ; CHECK-NEXT: isEntryFunction: true | ||||
| ; CHECK-NEXT: noSignedZerosFPMath: false | ; CHECK-NEXT: noSignedZerosFPMath: false | ||||
| ; CHECK-NEXT: memoryBound: false | ; CHECK-NEXT: memoryBound: false | ||||
| ; CHECK-NEXT: waveLimiter: false | ; CHECK-NEXT: waveLimiter: false | ||||
| ; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' | ; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' | ||||
| ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' | ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' | ||||
| ; CHECK-NEXT: frameOffsetReg: '$sgpr101' | ; CHECK-NEXT: frameOffsetReg: '$sgpr101' | ||||
| ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' | ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' | ||||
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