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llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
| Show First 20 Lines • Show All 909 Lines • ▼ Show 20 Lines | private: | ||||
| bool ParseDirectiveAMDKernelCodeT(); | bool ParseDirectiveAMDKernelCodeT(); | ||||
| bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const; | bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const; | ||||
| bool ParseDirectiveAMDGPUHsaKernel(); | bool ParseDirectiveAMDGPUHsaKernel(); | ||||
| bool ParseDirectiveISAVersion(); | bool ParseDirectiveISAVersion(); | ||||
| bool ParseDirectiveHSAMetadata(); | bool ParseDirectiveHSAMetadata(); | ||||
| bool ParseDirectivePALMetadataBegin(); | bool ParseDirectivePALMetadataBegin(); | ||||
| bool ParseDirectivePALMetadata(); | bool ParseDirectivePALMetadata(); | ||||
| bool ParseDirectiveAMDGPULDS(); | |||||
| /// Common code to parse out a block of text (typically YAML) between start and | /// Common code to parse out a block of text (typically YAML) between start and | ||||
| /// end directives. | /// end directives. | ||||
| bool ParseToEndDirective(const char *AssemblerDirectiveBegin, | bool ParseToEndDirective(const char *AssemblerDirectiveBegin, | ||||
| const char *AssemblerDirectiveEnd, | const char *AssemblerDirectiveEnd, | ||||
| std::string &CollectString); | std::string &CollectString); | ||||
| bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, | bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, | ||||
| ▲ Show 20 Lines • Show All 2,987 Lines • ▼ Show 20 Lines | for (;;) { | ||||
| PALMetadata->setRegister(Key, Value); | PALMetadata->setRegister(Key, Value); | ||||
| if (getLexer().isNot(AsmToken::Comma)) | if (getLexer().isNot(AsmToken::Comma)) | ||||
| break; | break; | ||||
| Lex(); | Lex(); | ||||
| } | } | ||||
| return false; | return false; | ||||
| } | } | ||||
| /// ParseDirectiveAMDGPULDS | |||||
| /// ::= .amdgpu_lds identifier ',' size_expression [',' align_expression] | |||||
| bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() { | |||||
| if (getParser().checkForValidSection()) | |||||
| return true; | |||||
| StringRef Name; | |||||
| SMLoc NameLoc = getLexer().getLoc(); | |||||
| if (getParser().parseIdentifier(Name)) | |||||
| return TokError("expected identifier in directive"); | |||||
| MCSymbol *Symbol = getContext().getOrCreateSymbol(Name); | |||||
| if (parseToken(AsmToken::Comma, "expected ','")) | |||||
| return true; | |||||
| unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI()); | |||||
| int64_t Size; | |||||
| SMLoc SizeLoc = getLexer().getLoc(); | |||||
| if (getParser().parseAbsoluteExpression(Size)) | |||||
| return true; | |||||
| if (Size < 0) | |||||
| return Error(SizeLoc, "size must be non-negative"); | |||||
| if (Size > LocalMemorySize) | |||||
| return Error(SizeLoc, "size is too large"); | |||||
| int64_t Align = 4; | |||||
| if (getLexer().is(AsmToken::Comma)) { | |||||
| Lex(); | |||||
| SMLoc AlignLoc = getLexer().getLoc(); | |||||
| if (getParser().parseAbsoluteExpression(Align)) | |||||
| return true; | |||||
| if (Align < 0 || !isPowerOf2_64(Align)) | |||||
| return Error(AlignLoc, "alignment must be a power of two"); | |||||
| // Alignment larger than the size of LDS is possible in theory, as long | |||||
| // as the linker manages to place to symbol at address 0, but we do want | |||||
| // to make sure the alignment fits nicely into a 32-bit integer. | |||||
| if (Align >= 1u << 31) | |||||
| return Error(AlignLoc, "alignment is too large"); | |||||
| } | |||||
| if (parseToken(AsmToken::EndOfStatement, | |||||
| "unexpected token in '.amdgpu_lds' directive")) | |||||
| return true; | |||||
| Symbol->redefineIfPossible(); | |||||
| if (!Symbol->isUndefined()) | |||||
| return Error(NameLoc, "invalid symbol redefinition"); | |||||
| getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align); | |||||
| return false; | |||||
| } | |||||
| bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) { | bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) { | ||||
| StringRef IDVal = DirectiveID.getString(); | StringRef IDVal = DirectiveID.getString(); | ||||
| if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { | if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { | ||||
| if (IDVal == ".amdgcn_target") | if (IDVal == ".amdgcn_target") | ||||
| return ParseDirectiveAMDGCNTarget(); | return ParseDirectiveAMDGCNTarget(); | ||||
| if (IDVal == ".amdhsa_kernel") | if (IDVal == ".amdhsa_kernel") | ||||
| Show All 17 Lines | if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { | ||||
| if (IDVal == ".amd_amdgpu_isa") | if (IDVal == ".amd_amdgpu_isa") | ||||
| return ParseDirectiveISAVersion(); | return ParseDirectiveISAVersion(); | ||||
| if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin) | if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin) | ||||
| return ParseDirectiveHSAMetadata(); | return ParseDirectiveHSAMetadata(); | ||||
| } | } | ||||
| if (IDVal == ".amdgpu_lds") | |||||
| return ParseDirectiveAMDGPULDS(); | |||||
| if (IDVal == PALMD::AssemblerDirectiveBegin) | if (IDVal == PALMD::AssemblerDirectiveBegin) | ||||
| return ParseDirectivePALMetadataBegin(); | return ParseDirectivePALMetadataBegin(); | ||||
| if (IDVal == PALMD::AssemblerDirective) | if (IDVal == PALMD::AssemblerDirective) | ||||
| return ParseDirectivePALMetadata(); | return ParseDirectivePALMetadata(); | ||||
| return true; | return true; | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 2,703 Lines • Show Last 20 Lines | |||||