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llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
| Show All 24 Lines | |||||
| /// ARM_AM - ARM Addressing Mode Stuff | /// ARM_AM - ARM Addressing Mode Stuff | ||||
| namespace ARM_AM { | namespace ARM_AM { | ||||
| enum ShiftOpc { | enum ShiftOpc { | ||||
| no_shift = 0, | no_shift = 0, | ||||
| asr, | asr, | ||||
| lsl, | lsl, | ||||
| lsr, | lsr, | ||||
| ror, | ror, | ||||
| rrx | rrx, | ||||
| uxtw | |||||
| }; | }; | ||||
| enum AddrOpc { | enum AddrOpc { | ||||
| sub = 0, | sub = 0, | ||||
| add | add | ||||
| }; | }; | ||||
| inline const char *getAddrOpcStr(AddrOpc Op) { return Op == sub ? "-" : ""; } | inline const char *getAddrOpcStr(AddrOpc Op) { return Op == sub ? "-" : ""; } | ||||
| inline const char *getShiftOpcStr(ShiftOpc Op) { | inline const char *getShiftOpcStr(ShiftOpc Op) { | ||||
| switch (Op) { | switch (Op) { | ||||
| default: llvm_unreachable("Unknown shift opc!"); | default: llvm_unreachable("Unknown shift opc!"); | ||||
| case ARM_AM::asr: return "asr"; | case ARM_AM::asr: return "asr"; | ||||
| case ARM_AM::lsl: return "lsl"; | case ARM_AM::lsl: return "lsl"; | ||||
| case ARM_AM::lsr: return "lsr"; | case ARM_AM::lsr: return "lsr"; | ||||
| case ARM_AM::ror: return "ror"; | case ARM_AM::ror: return "ror"; | ||||
| case ARM_AM::rrx: return "rrx"; | case ARM_AM::rrx: return "rrx"; | ||||
| case ARM_AM::uxtw: return "uxtw"; | |||||
| } | } | ||||
| } | } | ||||
| inline unsigned getShiftOpcEncoding(ShiftOpc Op) { | inline unsigned getShiftOpcEncoding(ShiftOpc Op) { | ||||
| switch (Op) { | switch (Op) { | ||||
| default: llvm_unreachable("Unknown shift opc!"); | default: llvm_unreachable("Unknown shift opc!"); | ||||
| case ARM_AM::asr: return 2; | case ARM_AM::asr: return 2; | ||||
| case ARM_AM::lsl: return 0; | case ARM_AM::lsl: return 0; | ||||
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