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llvm/test/CodeGen/PowerPC/negctr.ll
Show All 29 Lines | entry: | ||||
br i1 undef, label %for.end, label %for.body | br i1 undef, label %for.end, label %for.body | ||||
for.body: ; preds = %for.body, %entry | for.body: ; preds = %for.body, %entry | ||||
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] | %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ] | ||||
%indvars.iv.next = add i64 %indvars.iv, 1 | %indvars.iv.next = add i64 %indvars.iv, 1 | ||||
%exitcond = icmp eq i64 %indvars.iv.next, 0 | %exitcond = icmp eq i64 %indvars.iv.next, 0 | ||||
br i1 %exitcond, label %for.end, label %for.body | br i1 %exitcond, label %for.end, label %for.body | ||||
; FIXME: This should be a hardware loop. | |||||
shchenz: This is a known deg. With this patch,
Before `Codegen Prepare` Pass:
```
for.body… | |||||
Not Done ReplyInline ActionsYes, or teach SCEV about the uadd/usub pattern? I lean toward making SCEV smarter. hfinkel: Yes, or teach SCEV about the uadd/usub pattern? I lean toward making SCEV smarter. | |||||
Not Done ReplyInline Actions(and, just to clarify, that should be a separate patch, so the FIXME here is fine. although please add a note about the uadd/usub and GCP in the comment). hfinkel: (and, just to clarify, that should be a separate patch, so the FIXME here is fine. although… | |||||
; CHECK: @main1 | ; CHECK: @main1 | ||||
; CHECK: li [[REG:[0-9]+]], -1 | ; CHECK: li [[REG:[0-9]+]], 1 | ||||
; CHECK: mtctr [[REG]] | ; CHECK: addi [[REG2:[0-9]+]], [[REG]], 1 | ||||
; CHECK: bdnz | ; CHECK: cmpld | ||||
; CHECK: bge | |||||
for.end: ; preds = %for.body, %entry | for.end: ; preds = %for.body, %entry | ||||
ret void | ret void | ||||
} | } | ||||
define void @main2() #0 { | define void @main2() #0 { | ||||
entry: | entry: | ||||
br i1 undef, label %for.end, label %for.body | br i1 undef, label %for.end, label %for.body | ||||
Show All 37 Lines |
This is a known deg. With this patch,
Before Codegen Prepare Pass:
After Codegen Prepare Pass:
HardwareLoops Pass currently can not recognize uadd Intrinsic + extractvalue as a hardware loop(can not get loop exit count). Maybe we need to modify the logic in Codegen Prepare Pass: if the loop is a hardware loop, we should not optimize the cmp to uadd/usub intrinsic?