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Differential D50222 Diff 204851 test/CodeGen/AArch64/urem-seteq-vec-splat.ll

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test/CodeGen/AArch64/urem-seteq-vec-splat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
; Tests BuildUREMEqFold for 4 x i32 splat vectors with odd divisor. ; Tests BuildUREMEqFold for 4 x i32 splat vectors with odd divisor.
; See urem-seteq.ll for justification behind constants emitted. ; See urem-seteq.ll for justification behind constants emitted.
define <4 x i32> @test_urem_odd_vec_i32(<4 x i32> %X) nounwind readnone { define <4 x i32> @test_urem_odd_vec_i32(<4 x i32> %X) nounwind readnone {
; CHECK-LABEL: test_urem_odd_vec_i32: ; CHECK-LABEL: test_urem_odd_vec_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: mov w8, #52429
; CHECK-NEXT: movk w8, #52428, lsl #16 ; CHECK-NEXT: movk w8, #52428, lsl #16
; CHECK-NEXT: dup v2.4s, w8 ; CHECK-NEXT: dup v2.4s, w8
; CHECK-NEXT: umull2 v3.2d, v0.4s, v2.4s ; CHECK-NEXT: movi v1.16b, #51
; CHECK-NEXT: umull v2.2d, v0.2s, v2.2s ; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
; CHECK-NEXT: uzp2 v2.4s, v2.4s, v3.4s ; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
; CHECK-NEXT: movi v1.4s, #5
; CHECK-NEXT: ushr v2.4s, v2.4s, #2
; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
; CHECK-NEXT: movi v1.4s, #1 ; CHECK-NEXT: movi v1.4s, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 5, i32 5, i32 5, i32 5> %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 5, i32 5>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0> %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; Like test_urem_odd_vec_i32, but with 8 x i16 vectors. ; Like test_urem_odd_vec_i32, but with 8 x i16 vectors.
define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone { define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone {
; CHECK-LABEL: test_urem_odd_vec_i16: ; CHECK-LABEL: test_urem_odd_vec_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: mov w8, #52429
; CHECK-NEXT: dup v2.8h, w8 ; CHECK-NEXT: dup v2.8h, w8
; CHECK-NEXT: umull2 v3.4s, v0.8h, v2.8h ; CHECK-NEXT: movi v1.16b, #51
; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h ; CHECK-NEXT: mul v0.8h, v0.8h, v2.8h
; CHECK-NEXT: uzp2 v2.8h, v2.8h, v3.8h ; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h
; CHECK-NEXT: movi v1.8h, #5
; CHECK-NEXT: ushr v2.8h, v2.8h, #2
; CHECK-NEXT: mls v0.8h, v2.8h, v1.8h
; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
; CHECK-NEXT: movi v1.8h, #1 ; CHECK-NEXT: movi v1.8h, #1
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%urem = urem <8 x i16> %X, <i16 5, i16 5, i16 5, i16 5, %urem = urem <8 x i16> %X, <i16 5, i16 5, i16 5, i16 5,
i16 5, i16 5, i16 5, i16 5> i16 5, i16 5, i16 5, i16 5>
%cmp = icmp eq <8 x i16> %urem, <i16 0, i16 0, i16 0, i16 0, %cmp = icmp eq <8 x i16> %urem, <i16 0, i16 0, i16 0, i16 0,
i16 0, i16 0, i16 0, i16 0> i16 0, i16 0, i16 0, i16 0>
%ret = zext <8 x i1> %cmp to <8 x i16> %ret = zext <8 x i1> %cmp to <8 x i16>
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