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llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
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| Show First 20 Lines • Show All 1,277 Lines • ▼ Show 20 Lines | for (MVT VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, | ||||
| setOperationAction(ISD::BUILD_VECTOR, VT, Custom); | setOperationAction(ISD::BUILD_VECTOR, VT, Custom); | ||||
| setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); | setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); | ||||
| setOperationAction(ISD::VSELECT, VT, Custom); | setOperationAction(ISD::VSELECT, VT, Custom); | ||||
| setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); | setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); | ||||
| setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); | setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); | ||||
| setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); | setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); | ||||
| setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); | setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); | ||||
| setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); | setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); | ||||
| setOperationAction(ISD::STORE, VT, Custom); | |||||
| } | } | ||||
| if (HasInt256) | if (HasInt256) | ||||
| setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); | setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); | ||||
| if (HasInt256) { | if (HasInt256) { | ||||
| // Custom legalize 2x32 to get a little better code. | // Custom legalize 2x32 to get a little better code. | ||||
| setOperationAction(ISD::MGATHER, MVT::v2f32, Custom); | setOperationAction(ISD::MGATHER, MVT::v2f32, Custom); | ||||
| ▲ Show 20 Lines • Show All 19,774 Lines • ▼ Show 20 Lines | if (StoredVal.getValueType().isVector() && | ||||
| return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(), | return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(), | ||||
| St->getPointerInfo(), St->getAlignment(), | St->getPointerInfo(), St->getAlignment(), | ||||
| St->getMemOperand()->getFlags()); | St->getMemOperand()->getFlags()); | ||||
| } | } | ||||
| if (St->isTruncatingStore()) | if (St->isTruncatingStore()) | ||||
| return SDValue(); | return SDValue(); | ||||
| // If this is a 256-bit store of concatenated ops, we are better off splitting | |||||
| // that store into two 128-bit stores. This avoids spurious use of 256-bit ops | |||||
| // and each half can execute independently. Some cores would split the op into | |||||
| // halves anyway, so the concat (vinsertf128) is purely an extra op. | |||||
| MVT StoreVT = StoredVal.getSimpleValueType(); | MVT StoreVT = StoredVal.getSimpleValueType(); | ||||
| if (StoreVT.is256BitVector()) { | |||||
| if (StoredVal.getOpcode() != ISD::CONCAT_VECTORS || !StoredVal.hasOneUse()) | |||||
| return SDValue(); | |||||
| return split256BitStore(St, DAG); | |||||
| } | |||||
| assert(StoreVT.isVector() && StoreVT.getSizeInBits() == 64 && | assert(StoreVT.isVector() && StoreVT.getSizeInBits() == 64 && | ||||
| "Unexpected VT"); | "Unexpected VT"); | ||||
| if (DAG.getTargetLoweringInfo().getTypeAction(*DAG.getContext(), StoreVT) != | if (DAG.getTargetLoweringInfo().getTypeAction(*DAG.getContext(), StoreVT) != | ||||
| TargetLowering::TypeWidenVector) | TargetLowering::TypeWidenVector) | ||||
| return SDValue(); | return SDValue(); | ||||
| // Widen the vector, cast to a v2x64 type, extract the single 64-bit element | // Widen the vector, cast to a v2x64 type, extract the single 64-bit element | ||||
| // and store it. | // and store it. | ||||
| ▲ Show 20 Lines • Show All 23,588 Lines • Show Last 20 Lines | |||||