Differential D62847 Diff 202879 llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll

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ret void		ret void
}		}

; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of		; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of
; loop.		; loop.
define i64 @test_xaddrX4_loop(i8* %p) {		define i64 @test_xaddrX4_loop(i8* %p) {
; CHECK-LABEL: test_xaddrX4_loop:		; CHECK-LABEL: test_xaddrX4_loop:
; CHECK: # %bb.0: # %entry		; CHECK: # %bb.0: # %entry
		; CHECK-NEXT: li r5, 8
		; CHECK-NEXT: mtctr r5
; CHECK-NEXT: addi r4, r3, -8		; CHECK-NEXT: addi r4, r3, -8
; CHECK-NEXT: li r3, 8
; CHECK-NEXT: mtctr r3
; CHECK-NEXT: li r3, 0		; CHECK-NEXT: li r3, 0
; CHECK-NEXT: li r5, 3		; CHECK-NEXT: li r5, 3
; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.		; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4.
; CHECK-NEXT: .p2align 4		; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB4_1: # %for.body		; CHECK-NEXT: .LBB4_1: # %for.body
; CHECK: ldu r6, 8(r4)		; CHECK: ldu r6, 8(r4)
; CHECK-NEXT: ldx r7, r4, r5		; CHECK-NEXT: ldx r7, r4, r5
; CHECK-NEXT: maddld r3, r7, r6, r3		; CHECK-NEXT: maddld r3, r7, r6, r3
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