Please use GitHub pull requests for new patches. Phabricator shutdown timeline

Differential D58070 Diff 192859 llvm/trunk/test/CodeGen/AMDGPU/shl_add_ptr.ll

Changeset View

Standalone View

llvm/trunk/test/CodeGen/AMDGPU/shl_add_ptr.ll

Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Lines	define void @shl_add_ptr_combine_2use_both_max_private_offset(i16 zeroext %idx.arg) #0 {
%shl1 = shl i32 %idx.add, 5		%shl1 = shl i32 %idx.add, 5
%ptr0 = inttoptr i32 %shl0 to i32 addrspace(5)*		%ptr0 = inttoptr i32 %shl0 to i32 addrspace(5)*
%ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*		%ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*
store volatile i32 9, i32 addrspace(5)* %ptr0		store volatile i32 9, i32 addrspace(5)* %ptr0
store volatile i32 10, i32 addrspace(5)* %ptr1		store volatile i32 10, i32 addrspace(5)* %ptr1
ret void		ret void
}		}

		; FIXME: This or should fold into an offset on the write
; GCN-LABEL: {{^}}shl_or_ptr_combine_2use_lds:		; GCN-LABEL: {{^}}shl_or_ptr_combine_2use_lds:
; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0		; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0
; GCN: ds_write_b32 [[SCALE0]], v{{[0-9]+}} offset:32		; GCN: v_or_b32_e32 [[SCALE1:v[0-9]+]], 32, [[SCALE0]]
		; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+}}

; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0		; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0
; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+}} offset:64		; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+}} offset:64
define void @shl_or_ptr_combine_2use_lds(i32 %idx) #0 {		define void @shl_or_ptr_combine_2use_lds(i32 %idx) #0 {
%idx.add = or i32 %idx, 4		%idx.add = or i32 %idx, 4
%shl0 = shl i32 %idx.add, 3		%shl0 = shl i32 %idx.add, 3
%shl1 = shl i32 %idx.add, 4		%shl1 = shl i32 %idx.add, 4
%ptr0 = inttoptr i32 %shl0 to i32 addrspace(3)*		%ptr0 = inttoptr i32 %shl0 to i32 addrspace(3)*
Show All 25 Lines