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Differential D58070 Diff 192859 llvm/trunk/test/CodeGen/AMDGPU/calling-conventions.ll

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llvm/trunk/test/CodeGen/AMDGPU/calling-conventions.ll

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; SI: v_or_b32 ; SI: v_or_b32
define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) { define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) {
%add = add <2 x i16> %arg0, <i16 1, i16 1> %add = add <2 x i16> %arg0, <i16 1, i16 1>
store <2 x i16> %add, <2 x i16> addrspace(1)* undef store <2 x i16> %add, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}ps_mesa_inreg_v2i16: ; GCN-LABEL: {{^}}ps_mesa_inreg_v2i16:
; VI: s_lshr_b32 s1, s0, 16 ; VI: s_and_b32 s1, s0, 0xffff0000
; VI: s_add_i32 s1, s1, 1
; VI: s_add_i32 s0, s0, 1 ; VI: s_add_i32 s0, s0, 1
; VI: s_add_i32 s1, s1, 0x10000
; VI: s_and_b32 s0, s0, 0xffff ; VI: s_and_b32 s0, s0, 0xffff
; VI: s_lshl_b32 s1, s1, 16
; VI: s_or_b32 s0, s0, s1 ; VI: s_or_b32 s0, s0, s1
; VI: v_mov_b32_e32 v0, s0 ; VI: v_mov_b32_e32 v0, s0
; SI: s_lshl_b32 s1, s1, 16 ; SI: s_lshl_b32 s1, s1, 16
; SI: s_add_i32 s0, s0, 1 ; SI: s_add_i32 s0, s0, 1
; SI: s_add_i32 s1, s1, 0x10000 ; SI: s_add_i32 s1, s1, 0x10000
; SI: s_and_b32 s0, s0, 0xffff ; SI: s_and_b32 s0, s0, 0xffff
; SI: s_or_b32 s0, s0, s1 ; SI: s_or_b32 s0, s0, s1
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