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llvm/trunk/test/CodeGen/AMDGPU/shift-i64-opts.ll
Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines | define amdgpu_kernel void @lshr_i64_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { | ||||
store i64 %shl, i64 addrspace(1)* %out | store i64 %shl, i64 addrspace(1)* %out | ||||
ret void | ret void | ||||
} | } | ||||
; Make sure the and of the constant doesn't prevent bfe from forming | ; Make sure the and of the constant doesn't prevent bfe from forming | ||||
; after 64-bit shift is split. | ; after 64-bit shift is split. | ||||
; GCN-LABEL: {{^}}lshr_and_i64_35: | ; GCN-LABEL: {{^}}lshr_and_i64_35: | ||||
; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} | |||||
; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[HI]], 8, 23 | |||||
; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} | ; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} | ||||
; GCN: buffer_load_dword v[[LO:[0-9]+]] | |||||
; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[LO]], 8, 23 | |||||
; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} | ; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} | ||||
define amdgpu_kernel void @lshr_and_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { | define amdgpu_kernel void @lshr_and_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { | ||||
%val = load i64, i64 addrspace(1)* %in | %val = load i64, i64 addrspace(1)* %in | ||||
%and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff | %and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff | ||||
%shl = lshr i64 %and, 40 | %shl = lshr i64 %and, 40 | ||||
store i64 %shl, i64 addrspace(1)* %out | store i64 %shl, i64 addrspace(1)* %out | ||||
ret void | ret void | ||||
} | } | ||||
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