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Differential D58070 Diff 192859 llvm/trunk/test/CodeGen/AMDGPU/and.ll

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llvm/trunk/test/CodeGen/AMDGPU/and.ll

Show First 20 Lines • Show All 399 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64 ; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3ff00000 ; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3ff00000
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 4607182418800017408 %and = and i64 %a, 4607182418800017408
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64 ; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbff00000 ; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbff00000
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 13830554455654793216 %and = and i64 %a, 13830554455654793216
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64 ; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3fe00000 ; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3fe00000
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 4602678819172646912 %and = and i64 %a, 4602678819172646912
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64: ; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64:
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbfe00000 ; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbfe00000
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 13826050856027422720 %and = and i64 %a, 13826050856027422720
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64: ; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64:
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 2.0 ; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 2.0
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 4611686018427387904 %and = and i64 %a, 4611686018427387904
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64: ; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64:
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, -2.0 ; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, -2.0
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 13835058055282163712 %and = and i64 %a, 13835058055282163712
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64: ; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64:
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x40100000 ; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x40100000
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 4616189618054758400 %and = and i64 %a, 4616189618054758400
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64: ; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64:
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0 ; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xc0100000 ; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xc0100000
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 13839561654909534208 %and = and i64 %a, 13839561654909534208
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
Show All 26 Lines
define amdgpu_kernel void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, -1065353216 %and = and i64 %a, -1065353216
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; Shift into upper 32-bits ; Shift into upper 32-bits
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0 ; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 4647714815446351872 %and = and i64 %a, 4647714815446351872
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64: ; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64:
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: s_load_dwordx2 ; SI: s_load_dword
; SI-NOT: and ; SI-NOT: and
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0 ; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0
; SI-NOT: and ; SI-NOT: and
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { define amdgpu_kernel void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
%and = and i64 %a, 13871086852301127680 %and = and i64 %a, 13871086852301127680
store i64 %and, i64 addrspace(1)* %out, align 8 store i64 %and, i64 addrspace(1)* %out, align 8
ret void ret void
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }