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Differential D58070 Diff 192859 llvm/trunk/test/CodeGen/X86/sse3.ll

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llvm/trunk/test/CodeGen/X86/sse3.ll

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%tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
ret <16 x i8> %tmp9 ret <16 x i8> %tmp9
} }
; rdar://8520311 ; rdar://8520311
define <4 x i32> @t17() nounwind { define <4 x i32> @t17() nounwind {
; X86-LABEL: t17: ; X86-LABEL: t17:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] ; X86-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1]
; X86-NEXT: andpd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI.*}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: t17: ; X64-LABEL: t17:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] ; X64-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1]
; X64-NEXT: andpd {{.*}}(%rip), %xmm0 ; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%tmp1 = load <4 x float>, <4 x float>* undef, align 16 %tmp1 = load <4 x float>, <4 x float>* undef, align 16
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3> %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
%tmp3 = load <4 x float>, <4 x float>* undef, align 16 %tmp3 = load <4 x float>, <4 x float>* undef, align 16
%tmp4 = shufflevector <4 x float> %tmp2, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> %tmp4 = shufflevector <4 x float> %tmp2, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
%tmp5 = bitcast <4 x float> %tmp3 to <4 x i32> %tmp5 = bitcast <4 x float> %tmp3 to <4 x i32>
%tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
%tmp7 = and <4 x i32> %tmp6, <i32 undef, i32 undef, i32 -1, i32 0> %tmp7 = and <4 x i32> %tmp6, <i32 undef, i32 undef, i32 -1, i32 0>
ret <4 x i32> %tmp7 ret <4 x i32> %tmp7
} }