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Differential D57598 Diff 192599 llvm/trunk/test/Transforms/LoopVectorize/explicit_outer_detection.ll

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llvm/trunk/test/Transforms/LoopVectorize/explicit_outer_detection.ll

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; }		; }
; }		; }

; Case 1: Annotated outer loop WITH vector width information must be collected.		; Case 1: Annotated outer loop WITH vector width information must be collected.

; CHECK-LABEL: vector_width		; CHECK-LABEL: vector_width
; CHECK: LV: Loop hints: force=enabled width=4 unroll=0		; CHECK: LV: Loop hints: force=enabled width=4 unroll=0
; CHECK: LV: We can vectorize this outer loop!		; CHECK: LV: We can vectorize this outer loop!
; CHECK: LV: Using user VF 4.		; CHECK: LV: Using user VF 4 to build VPlans.
; CHECK-NOT: LV: Loop hints: force=?		; CHECK-NOT: LV: Loop hints: force=?
; CHECK-NOT: LV: Found a loop: inner.body		; CHECK-NOT: LV: Found a loop: inner.body

target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"		target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"

define void @vector_width(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr {		define void @vector_width(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr {
entry:		entry:
%cmp32 = icmp sgt i32 %N, 0		%cmp32 = icmp sgt i32 %N, 0
Show All 30 Lines	outer.inc: ; preds = %inner.body, %outer.body
%indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1		%indvars.iv.next36 = add nuw nsw i64 %indvars.iv35, 1
%exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count38		%exitcond39 = icmp eq i64 %indvars.iv.next36, %wide.trip.count38
br i1 %exitcond39, label %for.end15, label %outer.body, !llvm.loop !6		br i1 %exitcond39, label %for.end15, label %outer.body, !llvm.loop !6

for.end15: ; preds = %outer.inc, %entry		for.end15: ; preds = %outer.inc, %entry
ret void		ret void
}		}

; Case 2: Annotated outer loop WITHOUT vector width information doesn't have to		; Case 2: Annotated outer loop WITHOUT vector width information must be collected.
; be collected.

; CHECK-LABEL: case2		; CHECK-LABEL: case2
; CHECK-NOT: LV: Loop hints: force=enabled		; CHECK: LV: Loop hints: force=enabled width=0 unroll=0
; CHECK-NOT: LV: We can vectorize this outer loop!		; CHECK: LV: We can vectorize this outer loop!
; CHECK: LV: Loop hints: force=?		; CHECK: LV: Using computed VF 1 to build VPlans.
; CHECK: LV: Found a loop: inner.body

define void @case2(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr {		define void @case2(i32* nocapture %a, i32* nocapture readonly %b, i32 %N, i32 %M) local_unnamed_addr {
entry:		entry:
%cmp32 = icmp sgt i32 %N, 0		%cmp32 = icmp sgt i32 %N, 0
br i1 %cmp32, label %outer.ph, label %for.end15		br i1 %cmp32, label %outer.ph, label %for.end15

outer.ph: ; preds = %entry		outer.ph: ; preds = %entry
%cmp230 = icmp sgt i32 %M, 0		%cmp230 = icmp sgt i32 %M, 0
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