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Differential D59260 Diff 190273 llvm/test/CodeGen/PowerPC/f128-aggregates.ll

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llvm/test/CodeGen/PowerPC/f128-aggregates.ll

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; Since we can only pass a max of 8 float128 value in VSX registers, ensure we ; Since we can only pass a max of 8 float128 value in VSX registers, ensure we
; store to stack if passing more. ; store to stack if passing more.
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
align 16 %a) { align 16 %a) {
; CHECK-LABEL: testStruct_03: ; CHECK-LABEL: testStruct_03:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: std r10, 88(r1) ; CHECK-DAG: std r10, 88(r1)
; CHECK-NEXT: std r9, 80(r1) ; CHECK-DAG: std r9, 80(r1)
; CHECK-NEXT: std r8, 72(r1) ; CHECK-DAG: std r8, 72(r1)
; CHECK-NEXT: std r7, 64(r1) ; CHECK-DAG: std r7, 64(r1)
; CHECK-NEXT: std r6, 56(r1) ; CHECK-DAG: std r6, 56(r1)
; CHECK-NEXT: std r5, 48(r1) ; CHECK-DAG: std r5, 48(r1)
; CHECK-NEXT: std r4, 40(r1) ; CHECK-DAG: std r4, 40(r1)
; CHECK-NEXT: std r3, 32(r1) ; CHECK-DAG: std r3, 32(r1)
; CHECK-NEXT: lxv v2, 128(r1) ; CHECK-NEXT: lxv v2, 128(r1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: testStruct_03: ; CHECK-BE-LABEL: testStruct_03:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: std r10, 104(r1) ; CHECK-BE-DAG: std r10, 104(r1)
; CHECK-BE-NEXT: std r9, 96(r1) ; CHECK-BE-DAG: std r9, 96(r1)
; CHECK-BE-NEXT: std r8, 88(r1) ; CHECK-BE-DAG: std r8, 88(r1)
; CHECK-BE-NEXT: std r7, 80(r1) ; CHECK-BE-DAG: std r7, 80(r1)
; CHECK-BE-NEXT: std r6, 72(r1) ; CHECK-BE-DAG: std r6, 72(r1)
; CHECK-BE-NEXT: std r5, 64(r1) ; CHECK-BE-DAG: std r5, 64(r1)
; CHECK-BE-NEXT: std r4, 56(r1) ; CHECK-BE-DAG: std r4, 56(r1)
; CHECK-BE-NEXT: std r3, 48(r1) ; CHECK-BE-DAG: std r3, 48(r1)
; CHECK-BE-NEXT: lxv v2, 144(r1) ; CHECK-BE-NEXT: lxv v2, 144(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a7 = getelementptr inbounds %struct.With9fp128params, %a7 = getelementptr inbounds %struct.With9fp128params,
%struct.With9fp128params* %a, i64 0, i32 6 %struct.With9fp128params* %a, i64 0, i32 6
%0 = load fp128, fp128* %a7, align 16 %0 = load fp128, fp128* %a7, align 16
ret fp128 %0 ret fp128 %0
} }
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Linesentry:
ret fp128 %add3 ret fp128 %add3
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) { define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) {
; CHECK-LABEL: testNestedAggregate: ; CHECK-LABEL: testNestedAggregate:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: std r8, 72(r1) ; CHECK-DAG: std r10, 88(r1)
; CHECK-NEXT: std r7, 64(r1) ; CHECK-DAG: std r9, 80(r1)
; CHECK-NEXT: std r10, 88(r1) ; CHECK-DAG: std r8, 72(r1)
; CHECK-NEXT: std r9, 80(r1) ; CHECK-DAG: std r7, 64(r1)
; CHECK-NEXT: std r6, 56(r1) ; CHECK-DAG: std r6, 56(r1)
; CHECK-NEXT: std r5, 48(r1) ; CHECK-DAG: std r5, 48(r1)
; CHECK-NEXT: std r4, 40(r1) ; CHECK-DAG: std r4, 40(r1)
; CHECK-NEXT: std r3, 32(r1) ; CHECK-DAG: std r3, 32(r1)
; CHECK-NEXT: lxv v2, 64(r1) ; CHECK-NEXT: lxv v2, 64(r1)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: testNestedAggregate: ; CHECK-BE-LABEL: testNestedAggregate:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: std r8, 88(r1) ; CHECK-BE-DAG: std r8, 88(r1)
; CHECK-BE-NEXT: std r7, 80(r1) ; CHECK-BE-DAG: std r7, 80(r1)
; CHECK-BE-NEXT: std r10, 104(r1) ; CHECK-BE-DAG: std r10, 104(r1)
; CHECK-BE-NEXT: std r9, 96(r1) ; CHECK-BE-DAG: std r9, 96(r1)
; CHECK-BE-NEXT: std r6, 72(r1) ; CHECK-BE-DAG: std r6, 72(r1)
; CHECK-BE-NEXT: std r5, 64(r1) ; CHECK-BE-DAG: std r5, 64(r1)
; CHECK-BE-NEXT: std r4, 56(r1) ; CHECK-BE-DAG: std r4, 56(r1)
; CHECK-BE-NEXT: std r3, 48(r1) ; CHECK-BE-DAG: std r3, 48(r1)
; CHECK-BE-NEXT: lxv v2, 80(r1) ; CHECK-BE-NEXT: lxv v2, 80(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1 %c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
%0 = load fp128, fp128* %c, align 16 %0 = load fp128, fp128* %c, align 16
ret fp128 %0 ret fp128 %0
} }
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesentry:
%0 = bitcast i128 %a.coerce.fca.2.extract to fp128 %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
ret fp128 %0 ret fp128 %0
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define fp128 @sum_float128(i32 signext %count, ...) { define fp128 @sum_float128(i32 signext %count, ...) {
; CHECK-LABEL: sum_float128: ; CHECK-LABEL: sum_float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: std r10, 88(r1) ; CHECK-DAG: std r10, 88(r1)
; CHECK-NEXT: std r9, 80(r1) ; CHECK-DAG: std r9, 80(r1)
; CHECK-NEXT: std r8, 72(r1) ; CHECK-DAG: std r8, 72(r1)
; CHECK-NEXT: std r7, 64(r1) ; CHECK-DAG: std r7, 64(r1)
; CHECK-NEXT: std r6, 56(r1) ; CHECK-DAG: std r6, 56(r1)
; CHECK-NEXT: cmpwi cr0, r3, 1 ; CHECK-DAG: std r4, 40(r1)
; CHECK-NEXT: std r4, 40(r1) ; CHECK-DAG: cmpwi cr0, r3, 1
; CHECK-NEXT: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha ; CHECK-DAG: std r5, 48(r1)
; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l ; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
; CHECK-NEXT: lxvx v2, 0, [[REG1]] ; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
; CHECK-NEXT: std r5, 48(r1) ; CHECK-DAG: lxvx v2, 0, [[REG1]]
; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: addi r3, r1, 40 ; CHECK-NEXT: addi r3, r1, 40
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxvx v3, 0, r3
; CHECK-NEXT: xsaddqp v2, v3, v2 ; CHECK-NEXT: xsaddqp v2, v3, v2
; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72 ; CHECK-NEXT: addi [[REG2:r[0-9]+]], r1, 72
; CHECK-NEXT: std [[REG2]], -8(r1) ; CHECK-NEXT: std [[REG2]], -8(r1)
; CHECK-NEXT: lxv v3, 16(r3) ; CHECK-NEXT: lxv v3, 16(r3)
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