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llvm/test/CodeGen/ARM/memset-inline.ll
| Show All 19 Lines | |||||
| entry: | entry: | ||||
| ; CHECK-7A-LABEL: t2: | ; CHECK-7A-LABEL: t2: | ||||
| ; CHECK-7A: vmov.i32 {{q[0-9]+}}, #0x0 | ; CHECK-7A: vmov.i32 {{q[0-9]+}}, #0x0 | ||||
| ; CHECK-7A: movs r1, #10 | ; CHECK-7A: movs r1, #10 | ||||
| ; CHECK-7A: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2], r1 | ; CHECK-7A: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2], r1 | ||||
| ; CHECK-7A: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2] | ; CHECK-7A: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2] | ||||
| ; CHECK-6M-LABEL: t2: | ; CHECK-6M-LABEL: t2: | ||||
| ; CHECK-6M: movs [[REG:r[0-9]+]], #0 | ; CHECK-6M: movs [[REG:r[0-9]+]], #0 | ||||
| ; CHECK-6M: str [[REG]], [sp, #20] | ; CHECK-6M-DAG: str [[REG]], [sp, #20] | ||||
| ; CHECK-6M: str [[REG]], [sp, #16] | ; CHECK-6M-DAG: str [[REG]], [sp, #16] | ||||
| ; CHECK-6M: str [[REG]], [sp, #12] | ; CHECK-6M-DAG: str [[REG]], [sp, #12] | ||||
| ; CHECK-6M: str [[REG]], [sp, #8] | ; CHECK-6M-DAG: str [[REG]], [sp, #8] | ||||
| ; CHECK-6M: str [[REG]], [sp, #4] | ; CHECK-6M-DAG: str [[REG]], [sp, #4] | ||||
| ; CHECK-6M: str [[REG]], [sp] | ; CHECK-6M-DAG: str [[REG]], [sp] | ||||
| %buf = alloca [26 x i8], align 1 | %buf = alloca [26 x i8], align 1 | ||||
| %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0 | %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0 | ||||
| call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i1 false) | call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i1 false) | ||||
| call void @something(i8* %0) nounwind | call void @something(i8* %0) nounwind | ||||
| ret void | ret void | ||||
| } | } | ||||
| define void @t3(i8* %p) { | define void @t3(i8* %p) { | ||||
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