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Differential D59260 Diff 190273 llvm/test/CodeGen/AArch64/win64_vararg.ll

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llvm/test/CodeGen/AArch64/win64_vararg.ll

; RUN: llc < %s -mtriple=aarch64-pc-win32 | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-pc-win32 | FileCheck %s
define void @pass_va(i32 %count, ...) nounwind { define void @pass_va(i32 %count, ...) nounwind {
entry: entry:
; CHECK: str x30, [sp, #-80]! ; CHECK: str x30, [sp, #-80]!
; CHECK: add x8, sp, #24 ; CHECK: add x8, sp, #24
; CHECK: add x0, sp, #24 ; CHECK: add x0, sp, #24
; CHECK: stp x6, x7, [sp, #64] ; CHECK: stp x1, x2, [sp, #24]
; CHECK: stp x4, x5, [sp, #48] ; CHECK: stp x3, x4, [sp, #40]
; CHECK: stp x2, x3, [sp, #32] ; CHECK: stp x5, x6, [sp, #56]
; CHECK: str x1, [sp, #24] ; CHECK: str x7, [sp, #72]
; CHECK: str x8, [sp, #8] ; CHECK: str x8, [sp, #8]
; CHECK: bl other_func ; CHECK: bl other_func
; CHECK: ldr x30, [sp], #80 ; CHECK: ldr x30, [sp], #80
; CHECK: ret ; CHECK: ret
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%ap1 = bitcast i8** %ap to i8* %ap1 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap1) call void @llvm.va_start(i8* %ap1)
%ap2 = load i8*, i8** %ap, align 8 %ap2 = load i8*, i8** %ap, align 8
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesentry:
call void @llvm.va_start(i8* %ap1) call void @llvm.va_start(i8* %ap1)
%ap2 = load i8*, i8** %ap, align 8 %ap2 = load i8*, i8** %ap, align 8
ret i8* %ap2 ret i8* %ap2
} }
; CHECK-LABEL: copy1: ; CHECK-LABEL: copy1:
; CHECK: sub sp, sp, #80 ; CHECK: sub sp, sp, #80
; CHECK: add x8, sp, #24 ; CHECK: add x8, sp, #24
; CHECK: stp x6, x7, [sp, #64] ; CHECK: stp x1, x2, [sp, #24]
; CHECK: stp x4, x5, [sp, #48] ; CHECK: stp x3, x4, [sp, #40]
; CHECK: stp x2, x3, [sp, #32] ; CHECK: stp x5, x6, [sp, #56]
; CHECK: str x1, [sp, #24] ; CHECK: str x7, [sp, #72]
; CHECK: stp x8, x8, [sp], #80 ; CHECK: stp x8, x8, [sp], #80
; CHECK: ret ; CHECK: ret
define void @copy1(i64 %a0, ...) nounwind { define void @copy1(i64 %a0, ...) nounwind {
entry: entry:
%ap = alloca i8*, align 8 %ap = alloca i8*, align 8
%cp = alloca i8*, align 8 %cp = alloca i8*, align 8
%ap1 = bitcast i8** %ap to i8* %ap1 = bitcast i8** %ap to i8*
%cp1 = bitcast i8** %cp to i8* %cp1 = bitcast i8** %cp to i8*
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; CHECK: str x21, [sp, #-96]! ; CHECK: str x21, [sp, #-96]!
; CHECK: stp x19, x20, [sp, #16] ; CHECK: stp x19, x20, [sp, #16]
; CHECK: stp x29, x30, [sp, #32] ; CHECK: stp x29, x30, [sp, #32]
; CHECK: add x29, sp, #32 ; CHECK: add x29, sp, #32
; CHECK: add x8, x29, #24 ; CHECK: add x8, x29, #24
; CHECK: mov x19, x2 ; CHECK: mov x19, x2
; CHECK: mov x20, x1 ; CHECK: mov x20, x1
; CHECK: mov x21, x0 ; CHECK: mov x21, x0
; CHECK: stp x6, x7, [x29, #48] ; CHECK: stp x3, x4, [x29, #24]
; CHECK: stp x4, x5, [x29, #32] ; CHECK: stp x5, x6, [x29, #40]
; CHECK: str x3, [x29, #24] ; CHECK: str x7, [x29, #56]
; CHECK: str x8, [sp, #8] ; CHECK: str x8, [sp, #8]
; CHECK: bl __local_stdio_printf_options ; CHECK: bl __local_stdio_printf_options
; CHECK: ldr x8, [x0] ; CHECK: ldr x8, [x0]
; CHECK: add x5, x29, #24 ; CHECK: add x5, x29, #24
; CHECK: mov x1, x21 ; CHECK: mov x1, x21
; CHECK: mov x2, x20 ; CHECK: mov x2, x20
; CHECK: orr x0, x8, #0x2 ; CHECK: orr x0, x8, #0x2
; CHECK: mov x3, x19 ; CHECK: mov x3, x19
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; CHECK: add x29, sp, #48 ; CHECK: add x29, sp, #48
; CHECK: add x8, x29, #16 ; CHECK: add x8, x29, #16
; CHECK: stur x8, [x29, #-40] ; CHECK: stur x8, [x29, #-40]
; CHECK: mov w8, w0 ; CHECK: mov w8, w0
; CHECK: add x8, x8, #15 ; CHECK: add x8, x8, #15
; CHECK: lsr x15, x8, #4 ; CHECK: lsr x15, x8, #4
; CHECK: mov x19, x1 ; CHECK: mov x19, x1
; CHECK: mov [[REG2:x[0-9]+]], sp ; CHECK: mov [[REG2:x[0-9]+]], sp
; CHECK: stp x6, x7, [x29, #48]
; CHECK: stp x4, x5, [x29, #32]
; CHECK: stp x2, x3, [x29, #16] ; CHECK: stp x2, x3, [x29, #16]
; CHECK: stp x4, x5, [x29, #32]
; CHECK: stp x6, x7, [x29, #48]
; CHECK: bl __chkstk ; CHECK: bl __chkstk
; CHECK: mov x8, sp ; CHECK: mov x8, sp
; CHECK: sub [[REG:x[0-9]+]], x8, x15, lsl #4 ; CHECK: sub [[REG:x[0-9]+]], x8, x15, lsl #4
; CHECK: mov sp, [[REG]] ; CHECK: mov sp, [[REG]]
; CHECK: ldur [[REG3:x[0-9]+]], [x29, #-40] ; CHECK: ldur [[REG3:x[0-9]+]], [x29, #-40]
; CHECK: sxtw [[REG4:x[0-9]+]], w0 ; CHECK: sxtw [[REG4:x[0-9]+]], w0
; CHECK: bl __local_stdio_printf_options ; CHECK: bl __local_stdio_printf_options
; CHECK: ldr x8, [x0] ; CHECK: ldr x8, [x0]
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; CHECK-DAG: sub sp, sp, #96 ; CHECK-DAG: sub sp, sp, #96
; CHECK-DAG: str x21, [sp, #16] ; CHECK-DAG: str x21, [sp, #16]
; CHECK-DAG: stp x19, x20, [sp, #24] ; CHECK-DAG: stp x19, x20, [sp, #24]
; CHECK-DAG: str x30, [sp, #40] ; CHECK-DAG: str x30, [sp, #40]
; CHECK-DAG: add x8, sp, #56 ; CHECK-DAG: add x8, sp, #56
; CHECK-DAG: mov x19, x2 ; CHECK-DAG: mov x19, x2
; CHECK-DAG: mov x20, x1 ; CHECK-DAG: mov x20, x1
; CHECK-DAG: mov x21, x0 ; CHECK-DAG: mov x21, x0
; CHECK-DAG: stp x6, x7, [sp, #80] ; CHECK-DAG: stp x3, x4, [sp, #56]
; CHECK-DAG: stp x4, x5, [sp, #64] ; CHECK-DAG: stp x5, x6, [sp, #72]
; CHECK-DAG: str x3, [sp, #56] ; CHECK-DAG: str x7, [sp, #88]
; CHECK-DAG: str x8, [sp, #8] ; CHECK-DAG: str x8, [sp, #8]
; CHECK-DAG: bl __local_stdio_printf_options ; CHECK-DAG: bl __local_stdio_printf_options
; CHECK-DAG: ldr x8, [x0] ; CHECK-DAG: ldr x8, [x0]
; CHECK-DAG: add x5, sp, #56 ; CHECK-DAG: add x5, sp, #56
; CHECK-DAG: mov x1, x21 ; CHECK-DAG: mov x1, x21
; CHECK-DAG: mov x2, x20 ; CHECK-DAG: mov x2, x20
; CHECK-DAG: orr x0, x8, #0x2 ; CHECK-DAG: orr x0, x8, #0x2
; CHECK-DAG: mov x3, x19 ; CHECK-DAG: mov x3, x19
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