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llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
| ; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false -disable-post-ra < %s | FileCheck %s | ; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false -disable-post-ra < %s | FileCheck %s | ||||
| %va_list = type {i8*, i8*, i8*, i32, i32} | %va_list = type {i8*, i8*, i8*, i32, i32} | ||||
| @var = global %va_list zeroinitializer, align 8 | @var = global %va_list zeroinitializer, align 8 | ||||
| declare void @llvm.va_start(i8*) | declare void @llvm.va_start(i8*) | ||||
| define void @test_simple(i32 %n, ...) { | define void @test_simple(i32 %n, ...) { | ||||
| ; CHECK-LABEL: test_simple: | ; CHECK-LABEL: test_simple: | ||||
| ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] | ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] | ||||
| ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]] | ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]] | ||||
| ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var | ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var | ||||
| ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var | ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var | ||||
| ; CHECK: stp x1, x2, [sp, #[[GR_BASE:[0-9]+]]] | ; CHECK-DAG: stp x6, x7, [sp, # | ||||
| ; ... omit middle ones ... | ; ... omit middle ones ... | ||||
| ; CHECK: str x7, [sp, # | ; CHECK-DAG: str x1, [sp, #[[GR_BASE:[0-9]+]]] | ||||
| ; CHECK: stp q0, q1, [sp] | ; CHECK-DAG: stp q0, q1, [sp] | ||||
| ; ... omit middle ones ... | ; ... omit middle ones ... | ||||
| ; CHECK: stp q6, q7, [sp, # | ; CHECK-DAG: stp q6, q7, [sp, # | ||||
| ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]] | ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]] | ||||
| ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]] | ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]] | ||||
| ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #56 | ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #56 | ||||
| ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8] | ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8] | ||||
| ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp | ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp | ||||
| Show All 13 Lines | |||||
| define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { | define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { | ||||
| ; CHECK-LABEL: test_fewargs: | ; CHECK-LABEL: test_fewargs: | ||||
| ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] | ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] | ||||
| ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]] | ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]] | ||||
| ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var | ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var | ||||
| ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var | ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var | ||||
| ; CHECK: stp x3, x4, [sp, #[[GR_BASE:[0-9]+]]] | ; CHECK-DAG: stp x6, x7, [sp, # | ||||
| ; ... omit middle ones ... | ; ... omit middle ones ... | ||||
| ; CHECK: str x7, [sp, # | ; CHECK-DAG: str x3, [sp, #[[GR_BASE:[0-9]+]]] | ||||
| ; CHECK: stp q1, q2, [sp] | ; CHECK-DAG: stp q6, q7, [sp, #80] | ||||
| ; ... omit middle ones ... | ; ... omit middle ones ... | ||||
| ; CHECK: str q7, [sp, # | ; CHECK-DAG: str q1, [sp] | ||||
| ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]] | ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]] | ||||
| ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]] | ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]] | ||||
| ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40 | ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40 | ||||
| ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8] | ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8] | ||||
| ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp | ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp | ||||
| Show All 22 Lines | ; CHECK: str [[STACK]], [x[[VAR]]] | ||||
| ret void | ret void | ||||
| } | } | ||||
| ; If there are non-variadic arguments on the stack (here two i64s) then the | ; If there are non-variadic arguments on the stack (here two i64s) then the | ||||
| ; __stack field should point just past them. | ; __stack field should point just past them. | ||||
| define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) { | define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) { | ||||
| ; CHECK-LABEL: test_offsetstack: | ; CHECK-LABEL: test_offsetstack: | ||||
| ; CHECK: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #-80]! | |||||
| ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #96 | ; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #48] | ||||
| ; CHECK: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var | ; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #16] | ||||
| ; CHECK: str [[STACK_TOP]], [x[[VAR]]] | ; CHECK-DAG: str {{q[0-9]+}}, [sp] | ||||
| ; CHECK-DAG: add [[STACK_TOP:x[0-9]+]], sp, #96 | |||||
| ; CHECK-DAG: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var | |||||
| ; CHECK-DAG: str [[STACK_TOP]], [x[[VAR]]] | |||||
| %addr = bitcast %va_list* @var to i8* | %addr = bitcast %va_list* @var to i8* | ||||
| call void @llvm.va_start(i8* %addr) | call void @llvm.va_start(i8* %addr) | ||||
| ret void | ret void | ||||
| } | } | ||||
| declare void @llvm.va_end(i8*) | declare void @llvm.va_end(i8*) | ||||
| Show All 29 Lines | |||||