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Differential D42590 Diff 188707 llvm/trunk/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

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llvm/trunk/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

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; ;
; DISABLE: .[[ELSE_LABEL]]: # %if.else ; DISABLE: .[[ELSE_LABEL]]: # %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; DISABLE: slwi 3, 4, 1 ; DISABLE: slwi 3, 4, 1
; DISABLE: .[[EPILOG_BB]]: # %if.end ; DISABLE: .[[EPILOG_BB]]: # %if.end
; ;
; Epilogue code. ; Epilogue code.
; CHECK: mtlr {{[0-9]+}} ; CHECK: mtlr {{[0-9]+}}
; CHECK-NEXT: blr ; CHECK: blr
; ;
; ENABLE: .[[ELSE_LABEL]]: # %if.else ; ENABLE: .[[ELSE_LABEL]]: # %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; ENABLE: slwi 3, 4, 1 ; ENABLE: slwi 3, 4, 1
; ENABLE-NEXT: blr ; ENABLE-NEXT: blr
define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) { define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
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; CHECK-DAG: addi [[IV]], [[IV]], -1 ; CHECK-DAG: addi [[IV]], [[IV]], -1
; CHECK-DAG: add [[SUM]], 3, [[SUM]] ; CHECK-DAG: add [[SUM]], 3, [[SUM]]
; CHECK-NEXT: cmplwi [[IV]], 0 ; CHECK-NEXT: cmplwi [[IV]], 0
; CHECK-NEXT: bne 0, .[[LOOP]] ; CHECK-NEXT: bne 0, .[[LOOP]]
; ;
; Next BB ; Next BB
; CHECK: %for.exit ; CHECK: %for.exit
; CHECK: mtlr {{[0-9]+}} ; CHECK: mtlr {{[0-9]+}}
; CHECK-NEXT: blr ; CHECK: blr
define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) { define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
entry: entry:
br label %for.preheader br label %for.preheader
for.preheader: for.preheader:
tail call void asm "nop", ""() tail call void asm "nop", ""()
br label %for.body br label %for.body
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; ;
; ENABLE: cmplwi 0, 3, 0 ; ENABLE: cmplwi 0, 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Prologue code. ; Prologue code.
; Make sure we save the link register ; Make sure we save the link register
; CHECK: mflr {{[0-9]+}} ; CHECK: mflr {{[0-9]+}}
; ;
; DISABLE: cmplwi 0, 3, 0 ; DISABLE: std
; DISABLE-NEXT: std
; DISABLE-NEXT: std ; DISABLE-NEXT: std
; DISABLE: cmplwi 0, 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Loop preheader ; Loop preheader
; CHECK-DAG: li [[SUM:[0-9]+]], 0 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
; CHECK-DAG: li [[IV:[0-9]+]], 10 ; CHECK-DAG: li [[IV:[0-9]+]], 10
; ;
; Loop body ; Loop body
; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body ; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
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; ;
; DISABLE: .[[ELSE_LABEL]]: # %if.else ; DISABLE: .[[ELSE_LABEL]]: # %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; DISABLE: slwi 3, 4, 1 ; DISABLE: slwi 3, 4, 1
; ;
; DISABLE: .[[EPILOG_BB]]: # %if.end ; DISABLE: .[[EPILOG_BB]]: # %if.end
; Epilog code ; Epilog code
; CHECK: mtlr {{[0-9]+}} ; CHECK: mtlr {{[0-9]+}}
; CHECK-NEXT: blr ; CHECK: blr
; ;
; ENABLE: .[[ELSE_LABEL]]: # %if.else ; ENABLE: .[[ELSE_LABEL]]: # %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; ENABLE: slwi 3, 4, 1 ; ENABLE: slwi 3, 4, 1
; ENABLE-NEXT: blr ; ENABLE-NEXT: blr
define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) { define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
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; ;
; ENABLE: cmplwi 0, 3, 0 ; ENABLE: cmplwi 0, 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Prologue code. ; Prologue code.
; Make sure we save the link register ; Make sure we save the link register
; CHECK: mflr {{[0-9]+}} ; CHECK: mflr {{[0-9]+}}
; ;
; DISABLE: cmplwi 0, 3, 0 ; DISABLE: std
; DISABLE-NEXT: std
; DISABLE-NEXT: std ; DISABLE-NEXT: std
; DISABLE: cmplwi 0, 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; CHECK: bl somethingElse ; CHECK: bl somethingElse
; ;
; Loop preheader ; Loop preheader
; CHECK-DAG: li [[SUM:[0-9]+]], 0 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
; CHECK-DAG: li [[IV:[0-9]+]], 10 ; CHECK-DAG: li [[IV:[0-9]+]], 10
; ;
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; ;
; DISABLE: .[[ELSE_LABEL]]: # %if.else ; DISABLE: .[[ELSE_LABEL]]: # %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; DISABLE: slwi 3, 4, 1 ; DISABLE: slwi 3, 4, 1
; DISABLE: .[[EPILOG_BB]]: # %if.end ; DISABLE: .[[EPILOG_BB]]: # %if.end
; ;
; Epilogue code. ; Epilogue code.
; CHECK: mtlr {{[0-9]+}} ; CHECK: mtlr {{[0-9]+}}
; CHECK-NEXT: blr ; CHECK: blr
; ;
; ENABLE: .[[ELSE_LABEL]]: # %if.else ; ENABLE: .[[ELSE_LABEL]]: # %if.else
; Shift second argument by one and store into returned register. ; Shift second argument by one and store into returned register.
; ENABLE: slwi 3, 4, 1 ; ENABLE: slwi 3, 4, 1
; ENABLE-NEXT: blr ; ENABLE-NEXT: blr
define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind { define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind {
entry: entry:
%tobool = icmp eq i32 %cond, 0 %tobool = icmp eq i32 %cond, 0
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