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llvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll
| ; RUN: llc -mcpu cortex-a53 < %s | FileCheck %s | ; RUN: llc -mcpu cortex-a53 < %s | FileCheck %s | ||||
| target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128" | target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128" | ||||
| target triple = "aarch64--linux-gnu" | target triple = "aarch64--linux-gnu" | ||||
| declare void @f(i8*, i8*) | declare void @f(i8*, i8*) | ||||
| declare void @f2(i8*, i8*) | declare void @f2(i8*, i8*) | ||||
| declare void @_Z5setupv() | declare void @_Z5setupv() | ||||
| declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3 | declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) #3 | ||||
| define i32 @main() local_unnamed_addr #1 { | define i32 @main() local_unnamed_addr #1 { | ||||
| ; Make sure the stores happen in the correct order (the exact instructions could change). | ; Make sure the stores happen in the correct order (the exact instructions could change). | ||||
| ; CHECK-LABEL: main: | ; CHECK-LABEL: main: | ||||
| ; CHECK: str xzr, [sp, #80] | ; CHECK: orr w9, wzr, #0x1 | ||||
| ; CHECK: str w9, [sp, #80] | ; CHECK: str x9, [sp, #80] | ||||
| ; CHECK: stp q0, q0, [sp, #48] | ; CHECK: stp q0, q0, [sp, #48] | ||||
| ; CHECK: ldr w8, [sp, #48] | ; CHECK: ldr w8, [sp, #48] | ||||
| for.body.lr.ph.i.i.i.i.i.i63: | for.body.lr.ph.i.i.i.i.i.i63: | ||||
| %b1 = alloca [10 x i32], align 16 | %b1 = alloca [10 x i32], align 16 | ||||
| %x0 = bitcast [10 x i32]* %b1 to i8* | %x0 = bitcast [10 x i32]* %b1 to i8* | ||||
| %b2 = alloca [10 x i32], align 16 | %b2 = alloca [10 x i32], align 16 | ||||
| %x1 = bitcast [10 x i32]* %b2 to i8* | %x1 = bitcast [10 x i32]* %b2 to i8* | ||||
| Show All 24 Lines | |||||