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Differential D58096 Diff 187932 llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll

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llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll

; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
; SI-LABEL: {{^}}test_if: ; SI-LABEL: {{^}}test_if:
; Make sure the i1 values created by the cfg structurizer pass are ; Make sure the i1 values created by the cfg structurizer pass are
; moved using VALU instructions ; moved using VALU instructions
; waitcnt should be inserted after exec modification ; waitcnt should be inserted after exec modification
; SI: v_cmp_lt_i32_e32 vcc, 0, ; SI: v_cmp_lt_i32_e32 vcc, 1,
; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0 ; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0
; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0 ; SI-NEXT: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0
; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc ; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc
; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]] ; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]]
; SI-NEXT: ; mask branch [[FLOW_BB:BB[0-9]+_[0-9]+]] ; SI-NEXT: ; mask branch [[FLOW_BB:BB[0-9]+_[0-9]+]]
; SI-NEXT: s_cbranch_execz [[FLOW_BB]] ; SI-NEXT: s_cbranch_execz [[FLOW_BB]]
; SI-NEXT: BB{{[0-9]+}}_1: ; %LeafBlock3 ; SI-NEXT: BB{{[0-9]+}}_1: ; %LeafBlock3
; SI: s_mov_b64 s[{{[0-9]:[0-9]}}], -1 ; SI: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
; SI: s_and_saveexec_b64 ; SI: s_and_saveexec_b64
; SI-NEXT: ; mask branch ; SI-NEXT: ; mask branch
; v_mov should be after exec modification ; v_mov should be after exec modification
; SI: [[FLOW_BB]]: ; SI: [[FLOW_BB]]:
; SI-NEXT: s_or_saveexec_b64 [[SAVE3:s\[[0-9]+:[0-9]+\]]], [[SAVE2]] ; SI-NEXT: s_or_saveexec_b64 [[SAVE3:s\[[0-9]+:[0-9]+\]]], [[SAVE2]]
; SI-NEXT: s_xor_b64 exec, exec, [[SAVE3]] ; SI-NEXT: s_xor_b64 exec, exec, [[SAVE3]]
; SI-NEXT: ; mask branch ; SI-NEXT: ; mask branch
; ;
define amdgpu_kernel void @test_if(i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 { define amdgpu_kernel void @test_if(i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
switch i32 %tid, label %default [ switch i32 %tid, label %default [
i32 0, label %case0
i32 1, label %case1 i32 1, label %case1
i32 2, label %case2
] ]
case0: case1:
%arrayidx1 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b %arrayidx1 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
store i32 13, i32 addrspace(1)* %arrayidx1, align 4 store i32 13, i32 addrspace(1)* %arrayidx1, align 4
br label %end br label %end
case1: case2:
%arrayidx5 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b %arrayidx5 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
store i32 17, i32 addrspace(1)* %arrayidx5, align 4 store i32 17, i32 addrspace(1)* %arrayidx5, align 4
br label %end br label %end
default: default:
%cmp8 = icmp eq i32 %tid, 2 %cmp8 = icmp eq i32 %tid, 2
%arrayidx10 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b %arrayidx10 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b
br i1 %cmp8, label %if, label %else br i1 %cmp8, label %if, label %else
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