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# llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Line(s) | 53 | #endif | |||
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143 | case ISD::SUBE: | 143 | case ISD::SUBE: | ||

144 | case ISD::ADDCARRY: | 144 | case ISD::ADDCARRY: | ||

145 | case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break; | 145 | case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break; | ||

146 | 146 | | |||

147 | case ISD::SADDSAT: | 147 | case ISD::SADDSAT: | ||

148 | case ISD::UADDSAT: | 148 | case ISD::UADDSAT: | ||

149 | case ISD::SSUBSAT: | 149 | case ISD::SSUBSAT: | ||

150 | case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break; | 150 | case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break; | ||

151 | case ISD::SMULFIX: Res = PromoteIntRes_SMULFIX(N); break; | 151 | case ISD::SMULFIX: | ||

152 | case ISD::UMULFIX: Res = PromoteIntRes_MULFIX(N); break; | ||||

152 | 153 | | |||

153 | case ISD::ATOMIC_LOAD: | 154 | case ISD::ATOMIC_LOAD: | ||

154 | Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break; | 155 | Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break; | ||

155 | 156 | | |||

156 | case ISD::ATOMIC_LOAD_ADD: | 157 | case ISD::ATOMIC_LOAD_ADD: | ||

157 | case ISD::ATOMIC_LOAD_SUB: | 158 | case ISD::ATOMIC_LOAD_SUB: | ||

158 | case ISD::ATOMIC_LOAD_AND: | 159 | case ISD::ATOMIC_LOAD_AND: | ||

159 | case ISD::ATOMIC_LOAD_CLR: | 160 | case ISD::ATOMIC_LOAD_CLR: | ||

▲ Show 20 Lines • Show All 480 Lines • ▼ Show 20 Line(s) | 604 | SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSAT(SDNode *N) { | |||

640 | Op2Promoted = | 641 | Op2Promoted = | ||

641 | DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); | 642 | DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); | ||

642 | 643 | | |||

643 | SDValue Result = | 644 | SDValue Result = | ||

644 | DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted); | 645 | DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted); | ||

645 | return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); | 646 | return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); | ||

646 | } | 647 | } | ||

647 | 648 | | |||

648 | SDValue DAGTypeLegalizer::PromoteIntRes_SMULFIX(SDNode *N) { | 649 | SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) { | ||

649 | // Can just promote the operands then continue with operation. | 650 | // Can just promote the operands then continue with operation. | ||

650 | SDLoc dl(N); | 651 | SDLoc dl(N); | ||

651 | SDValue Op1Promoted = SExtPromotedInteger(N->getOperand(0)); | 652 | SDValue Op1Promoted, Op2Promoted; | ||

652 | SDValue Op2Promoted = SExtPromotedInteger(N->getOperand(1)); | 653 | if (N->getOpcode() == ISD::SMULFIX) { | ||

654 | Op1Promoted = SExtPromotedInteger(N->getOperand(0)); | ||||

655 | Op2Promoted = SExtPromotedInteger(N->getOperand(1)); | ||||

656 | } else { | ||||

657 | Op1Promoted = ZExtPromotedInteger(N->getOperand(0)); | ||||

658 | Op2Promoted = ZExtPromotedInteger(N->getOperand(1)); | ||||

659 | } | ||||

653 | EVT PromotedType = Op1Promoted.getValueType(); | 660 | EVT PromotedType = Op1Promoted.getValueType(); | ||

654 | return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted, | 661 | return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted, | ||

655 | N->getOperand(2)); | 662 | N->getOperand(2)); | ||

656 | } | 663 | } | ||

657 | 664 | | |||

658 | SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { | 665 | SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { | ||

659 | if (ResNo == 1) | 666 | if (ResNo == 1) | ||

660 | return PromoteIntRes_Overflow(N); | 667 | return PromoteIntRes_Overflow(N); | ||

▲ Show 20 Lines • Show All 424 Lines • ▼ Show 20 Line(s) | 1031 | bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { | |||

1085 | case ISD::ADDCARRY: | 1092 | case ISD::ADDCARRY: | ||

1086 | case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break; | 1093 | case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break; | ||

1087 | 1094 | | |||

1088 | case ISD::FRAMEADDR: | 1095 | case ISD::FRAMEADDR: | ||

1089 | case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break; | 1096 | case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break; | ||

1090 | 1097 | | |||

1091 | case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break; | 1098 | case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break; | ||

1092 | 1099 | | |||

1093 | case ISD::SMULFIX: Res = PromoteIntOp_SMULFIX(N); break; | 1100 | case ISD::SMULFIX: | ||

1101 | case ISD::UMULFIX: Res = PromoteIntOp_MULFIX(N); break; | ||||

1094 | 1102 | | |||

1095 | case ISD::FPOWI: Res = PromoteIntOp_FPOWI(N); break; | 1103 | case ISD::FPOWI: Res = PromoteIntOp_FPOWI(N); break; | ||

1096 | } | 1104 | } | ||

1097 | 1105 | | |||

1098 | // If the result is null, the sub-method took care of registering results etc. | 1106 | // If the result is null, the sub-method took care of registering results etc. | ||

1099 | if (!Res.getNode()) return false; | 1107 | if (!Res.getNode()) return false; | ||

1100 | 1108 | | |||

1101 | // If the result is N, the sub-method updated N in place. Tell the legalizer | 1109 | // If the result is N, the sub-method updated N in place. Tell the legalizer | ||

▲ Show 20 Lines • Show All 345 Lines • ▼ Show 20 Line(s) | 1438 | SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) { | |||

1447 | case TargetLoweringBase::ZeroOrNegativeOneBooleanContent: | 1455 | case TargetLoweringBase::ZeroOrNegativeOneBooleanContent: | ||

1448 | Carry = DAG.getSExtOrTrunc(Carry, DL, VT); | 1456 | Carry = DAG.getSExtOrTrunc(Carry, DL, VT); | ||

1449 | break; | 1457 | break; | ||

1450 | } | 1458 | } | ||

1451 | 1459 | | |||

1452 | return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0); | 1460 | return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0); | ||

1453 | } | 1461 | } | ||

1454 | 1462 | | |||

1455 | SDValue DAGTypeLegalizer::PromoteIntOp_SMULFIX(SDNode *N) { | 1463 | SDValue DAGTypeLegalizer::PromoteIntOp_MULFIX(SDNode *N) { | ||

1456 | SDValue Op2 = ZExtPromotedInteger(N->getOperand(2)); | 1464 | SDValue Op2 = ZExtPromotedInteger(N->getOperand(2)); | ||

1457 | return SDValue( | 1465 | return SDValue( | ||

1458 | DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0); | 1466 | DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0); | ||

1459 | } | 1467 | } | ||

1460 | 1468 | | |||

1461 | SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) { | 1469 | SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) { | ||

1462 | // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width. | 1470 | // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width. | ||

1463 | SDValue Op = ZExtPromotedInteger(N->getOperand(0)); | 1471 | SDValue Op = ZExtPromotedInteger(N->getOperand(0)); | ||

▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Line(s) | 1515 | #endif | |||

1615 | case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; | 1623 | case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; | ||

1616 | case ISD::UMULO: | 1624 | case ISD::UMULO: | ||

1617 | case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; | 1625 | case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; | ||

1618 | 1626 | | |||

1619 | case ISD::SADDSAT: | 1627 | case ISD::SADDSAT: | ||

1620 | case ISD::UADDSAT: | 1628 | case ISD::UADDSAT: | ||

1621 | case ISD::SSUBSAT: | 1629 | case ISD::SSUBSAT: | ||

1622 | case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break; | 1630 | case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break; | ||

1623 | case ISD::SMULFIX: ExpandIntRes_SMULFIX(N, Lo, Hi); break; | 1631 | case ISD::SMULFIX: | ||

1632 | case ISD::UMULFIX: ExpandIntRes_MULFIX(N, Lo, Hi); break; | ||||

1624 | } | 1633 | } | ||

1625 | 1634 | | |||

1626 | // If Lo/Hi is null, the sub-method took care of registering results etc. | 1635 | // If Lo/Hi is null, the sub-method took care of registering results etc. | ||

1627 | if (Lo.getNode()) | 1636 | if (Lo.getNode()) | ||

1628 | SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); | 1637 | SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); | ||

1629 | } | 1638 | } | ||

1630 | 1639 | | |||

1631 | /// Lower an atomic node to the appropriate builtin call. | 1640 | /// Lower an atomic node to the appropriate builtin call. | ||

▲ Show 20 Lines • Show All 951 Lines • ▼ Show 20 Line(s) | |||||

2583 | } | 2592 | } | ||

2584 | 2593 | | |||

2585 | void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo, | 2594 | void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo, | ||

2586 | SDValue &Hi) { | 2595 | SDValue &Hi) { | ||

2587 | SDValue Result = TLI.expandAddSubSat(N, DAG); | 2596 | SDValue Result = TLI.expandAddSubSat(N, DAG); | ||

2588 | SplitInteger(Result, Lo, Hi); | 2597 | SplitInteger(Result, Lo, Hi); | ||

2589 | } | 2598 | } | ||

2590 | 2599 | | |||

2591 | void DAGTypeLegalizer::ExpandIntRes_SMULFIX(SDNode *N, SDValue &Lo, | 2600 | void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo, | ||

2592 | SDValue &Hi) { | 2601 | SDValue &Hi) { | ||

2602 | assert( | ||||

2603 | (N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::UMULFIX) && | ||||

2604 | "Expected operand to be signed or unsigned fixed point multiplication"); | ||||

2605 | | ||||

2593 | SDLoc dl(N); | 2606 | SDLoc dl(N); | ||

2594 | EVT VT = N->getValueType(0); | 2607 | EVT VT = N->getValueType(0); | ||

2595 | SDValue LHS = N->getOperand(0); | 2608 | SDValue LHS = N->getOperand(0); | ||

2596 | SDValue RHS = N->getOperand(1); | 2609 | SDValue RHS = N->getOperand(1); | ||

2597 | uint64_t Scale = N->getConstantOperandVal(2); | 2610 | uint64_t Scale = N->getConstantOperandVal(2); | ||

2598 | if (!Scale) { | 2611 | if (!Scale) { | ||

2599 | SDValue Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); | 2612 | SDValue Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); | ||

2600 | SplitInteger(Result, Lo, Hi); | 2613 | SplitInteger(Result, Lo, Hi); | ||

2601 | return; | 2614 | return; | ||

2602 | } | 2615 | } | ||

2603 | 2616 | | |||

2604 | EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); | 2617 | EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); | ||

2605 | SDValue LL, LH, RL, RH; | 2618 | SDValue LL, LH, RL, RH; | ||

2606 | GetExpandedInteger(LHS, LL, LH); | 2619 | GetExpandedInteger(LHS, LL, LH); | ||

2607 | GetExpandedInteger(RHS, RL, RH); | 2620 | GetExpandedInteger(RHS, RL, RH); | ||

2608 | SmallVector<SDValue, 4> Result; | 2621 | SmallVector<SDValue, 4> Result; | ||

2609 | 2622 | | |||

2610 | if (!TLI.expandMUL_LOHI(ISD::SMUL_LOHI, VT, dl, LHS, RHS, Result, NVT, DAG, | 2623 | bool Signed = N->getOpcode() == ISD::SMULFIX; | ||

2624 | unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI; | ||||

2625 | if (!TLI.expandMUL_LOHI(LoHiOp, VT, dl, LHS, RHS, Result, NVT, DAG, | ||||

2611 | TargetLowering::MulExpansionKind::OnlyLegalOrCustom, | 2626 | TargetLowering::MulExpansionKind::OnlyLegalOrCustom, | ||

2612 | LL, LH, RL, RH)) { | 2627 | LL, LH, RL, RH)) { | ||

2613 | report_fatal_error("Unable to expand SMUL_FIX using SMUL_LOHI."); | 2628 | report_fatal_error("Unable to expand MUL_FIX using MUL_LOHI."); | ||

2614 | return; | 2629 | return; | ||

2615 | } | 2630 | } | ||

2616 | 2631 | | |||

2617 | unsigned VTSize = VT.getScalarSizeInBits(); | 2632 | unsigned VTSize = VT.getScalarSizeInBits(); | ||

2618 | unsigned NVTSize = NVT.getScalarSizeInBits(); | 2633 | unsigned NVTSize = NVT.getScalarSizeInBits(); | ||

2619 | EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); | 2634 | EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); | ||

2620 | 2635 | | |||

2621 | // Shift whole amount by scale. | 2636 | // Shift whole amount by scale. | ||

▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Line(s) | 2675 | } else if (Scale < VTSize) { | |||

2666 | SDValue SRLAmnt = DAG.getConstant(Scale - NVTSize, dl, ShiftTy); | 2681 | SDValue SRLAmnt = DAG.getConstant(Scale - NVTSize, dl, ShiftTy); | ||

2667 | SDValue SHLAmnt = DAG.getConstant(VTSize - Scale, dl, ShiftTy); | 2682 | SDValue SHLAmnt = DAG.getConstant(VTSize - Scale, dl, ShiftTy); | ||

2668 | Lo = DAG.getNode(ISD::SRL, dl, NVT, ResultLH, SRLAmnt); | 2683 | Lo = DAG.getNode(ISD::SRL, dl, NVT, ResultLH, SRLAmnt); | ||

2669 | Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, | 2684 | Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, | ||

2670 | DAG.getNode(ISD::SHL, dl, NVT, ResultHL, SHLAmnt)); | 2685 | DAG.getNode(ISD::SHL, dl, NVT, ResultHL, SHLAmnt)); | ||

2671 | Hi = DAG.getNode(ISD::SRL, dl, NVT, ResultHL, SRLAmnt); | 2686 | Hi = DAG.getNode(ISD::SRL, dl, NVT, ResultHL, SRLAmnt); | ||

2672 | Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, | 2687 | Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, | ||

2673 | DAG.getNode(ISD::SHL, dl, NVT, ResultHH, SHLAmnt)); | 2688 | DAG.getNode(ISD::SHL, dl, NVT, ResultHH, SHLAmnt)); | ||

2689 | } else if (Scale == VTSize) { | ||||

2690 | assert( | ||||

2691 | !Signed && | ||||

2692 | "Only unsigned types can have a scale equal to the operand bit width"); | ||||

2693 | | ||||

2694 | Lo = ResultHL; | ||||

2695 | Hi = ResultHH; | ||||

2674 | } else { | 2696 | } else { | ||

2675 | llvm_unreachable( | 2697 | llvm_unreachable("Expected the scale to be less than or equal to the width " | ||

2676 | "Expected the scale to be less than the width of the operands"); | 2698 | "of the operands"); | ||

2677 | } | 2699 | } | ||

2678 | } | 2700 | } | ||

2679 | 2701 | | |||

2680 | void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, | 2702 | void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, | ||

2681 | SDValue &Lo, SDValue &Hi) { | 2703 | SDValue &Lo, SDValue &Hi) { | ||

2682 | SDValue LHS = Node->getOperand(0); | 2704 | SDValue LHS = Node->getOperand(0); | ||

2683 | SDValue RHS = Node->getOperand(1); | 2705 | SDValue RHS = Node->getOperand(1); | ||

2684 | SDLoc dl(Node); | 2706 | SDLoc dl(Node); | ||

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