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llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
| Show First 20 Lines • Show All 1,769 Lines • ▼ Show 20 Lines | def DB_UPD : | ||||
| let Inst{20} = L_bit; | let Inst{20} = L_bit; | ||||
| let Inst{19-16} = Rn; | let Inst{19-16} = Rn; | ||||
| let Inst{15-0} = regs; | let Inst{15-0} = regs; | ||||
| } | } | ||||
| } | } | ||||
| let hasSideEffects = 0 in { | let hasSideEffects = 0 in { | ||||
| let mayLoad = 1, hasExtraDefRegAllocReq = 1 in | let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in | ||||
| defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; | defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; | ||||
| multiclass thumb2_st_mult<string asm, InstrItinClass itin, | multiclass thumb2_st_mult<string asm, InstrItinClass itin, | ||||
| InstrItinClass itin_upd, bit L_bit> { | InstrItinClass itin_upd, bit L_bit> { | ||||
| def IA : | def IA : | ||||
| T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), | T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), | ||||
| itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { | itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { | ||||
| bits<4> Rn; | bits<4> Rn; | ||||
| ▲ Show 20 Lines • Show All 3,103 Lines • Show Last 20 Lines | |||||