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llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
| Show First 20 Lines • Show All 619 Lines • ▼ Show 20 Lines | void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, | ||||
| if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq) | if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq) | ||||
| OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)"; | OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)"; | ||||
| if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq) | if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq) | ||||
| OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)"; | OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)"; | ||||
| if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; | if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; | ||||
| if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)"; | if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)"; | ||||
| if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; | if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; | ||||
| if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)"; | if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)"; | ||||
| if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)"; | |||||
| // Emit all of the target-specific flags... | // Emit all of the target-specific flags... | ||||
| BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); | BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); | ||||
| if (!TSF) | if (!TSF) | ||||
| PrintFatalError("no TSFlags?"); | PrintFatalError("no TSFlags?"); | ||||
| uint64_t Value = 0; | uint64_t Value = 0; | ||||
| for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { | for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { | ||||
| if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i))) | if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i))) | ||||
| ▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines | |||||