Differential D54853 Diff 176332 llvm/trunk/include/llvm/MC/MCInstrDesc.h

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llvm/trunk/include/llvm/MC/MCInstrDesc.h

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines	enum Flag {
CheapAsAMove,		CheapAsAMove,
ExtraSrcRegAllocReq,		ExtraSrcRegAllocReq,
ExtraDefRegAllocReq,		ExtraDefRegAllocReq,
RegSequence,		RegSequence,
ExtractSubreg,		ExtractSubreg,
InsertSubreg,		InsertSubreg,
Convergent,		Convergent,
Add,		Add,
Trap		Trap,
		VariadicOpsAreDefs,
};		};
}		}

/// Describe properties that are true of each instruction in the target		/// Describe properties that are true of each instruction in the target
/// description file. This captures information about side effects, register		/// description file. This captures information about side effects, register
/// use and many other things. There is one instance of this struct for each		/// use and many other things. There is one instance of this struct for each
/// target instruction class, and the MachineInstr class points to this struct		/// target instruction class, and the MachineInstr class points to this struct
/// directly to describe itself.		/// directly to describe itself.
▲ Show 20 Lines • Show All 215 Lines • ▼ Show 20 Lines	public:


/// Return true if this instruction is convergent.		/// Return true if this instruction is convergent.
///		///
/// Convergent instructions may not be made control-dependent on any		/// Convergent instructions may not be made control-dependent on any
/// additional values.		/// additional values.
bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }		bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }

		/// Return true if variadic operands of this instruction are definitions.
		bool variadicOpsAreDefs() const {
		return Flags & (1ULL << MCID::VariadicOpsAreDefs);
		}

//===--------------------------------------------------------------------===//		//===--------------------------------------------------------------------===//
// Side Effect Analysis		// Side Effect Analysis
//===--------------------------------------------------------------------===//		//===--------------------------------------------------------------------===//

/// Return true if this instruction could possibly read memory.		/// Return true if this instruction could possibly read memory.
/// Instructions with this flag set are not necessarily simple load		/// Instructions with this flag set are not necessarily simple load
/// instructions, they may load a value and modify it, for example.		/// instructions, they may load a value and modify it, for example.
bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }		bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
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