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Differential D6023 Diff 15850 test/CodeGen/Mips/inlineasm-operand-code.ll

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test/CodeGen/Mips/inlineasm-operand-code.ll

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;CHECK_LITTLE_32: #NO_APP ;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ; tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ;
; z with 0 ; z with 0
;CHECK_LITTLE_32: #APP ;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0 ;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0
;CHECK_LITTLE_32: #NO_APP ;CHECK_LITTLE_32: #NO_APP
tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
; z with non-zero and the "r"(register) and "J"(integer zero) constraints
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
dsandersUnsubmitted
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$0 shouldn't be permitted

dsanders: $0 shouldn't be permitted
;CHECK_LITTLE_32: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
; z with zero and the "r"(register) and "J"(integer zero) constraints
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: mtc0 $0, ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
; z with non-zero and just the "r"(register) constraint
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
dsandersUnsubmitted
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$0 shouldn't be permitted

dsanders: $0 shouldn't be permitted
;CHECK_LITTLE_32: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
; z with zero and just the "r"(register) constraint
; FIXME: Check for $0, instead of other registers.
; We should be using $0 directly in this case, not real registers.
dsandersUnsubmitted
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Shouldn't this be restricted to $0?

dsanders: Shouldn't this be restricted to $0?
tomatabacuAuthorUnsubmitted
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No, because in this case we no longer have the "J" constraint (which makes zero-values into immediates), so the value is always put into a register.

tomatabacu: No, because in this case we no longer have the "J" constraint (which makes zero-values into…
dsandersUnsubmitted
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The reason I think it should be $0 is that materializing 0 can be done without any code. Whereas the above examples passes in the immediate 0 and printed it as $0, in this code I believe this one should be passing in the register $0.

As we discussed off-list, the code generator is currently materializing 0 with 'addiu $1, $zero, 0'. We need to fix this but it's not related to your patch.

For now, could you add an explicit check for the 'addiu ${{[0-9]+}}, $zero, 0' along with a fixme comment explaining the issue. This way, we will be prompted to correct the test when we fix the materialization problem.

dsanders: The reason I think it should be $0 is that materializing 0 can be done without any code.
tomatabacuAuthorUnsubmitted
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There's no need for an additional check for addiu, as the test would already fail if the materialization of 0 was fixed.
This is because, for the first argument of the mtc0 instruction, we're checking for any register that is not $0, so if the currently non-$0 register changes into $0, the test will fail.

I'll still add a FIXME with an explanation, though.

tomatabacu: There's no need for an additional check for addiu, as the test would already fail if the…
dsandersUnsubmitted
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Good point. LGTM.

dsanders: Good point. LGTM.
; When the materialization of 0 gets fixed, this test will fail.
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
ret i32 0 ret i32 0
} }
; a long long in 32 bit mode (use to assert) ; a long long in 32 bit mode (use to assert)
define i32 @constraint_longlong() nounwind { define i32 @constraint_longlong() nounwind {
entry: entry:
;CHECK_LITTLE_32-LABEL: constraint_longlong: ;CHECK_LITTLE_32-LABEL: constraint_longlong:
;CHECK_LITTLE_32: #APP ;CHECK_LITTLE_32: #APP
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