Differential D49266 Diff 155411 include/llvm/CodeGen/TargetLowering.h

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include/llvm/CodeGen/TargetLowering.h

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/// Shifts: x >> y << y		/// Shifts: x >> y << y
/// Return true if the variant with 2 shifts is preferred.		/// Return true if the variant with 2 shifts is preferred.
/// Return false if there is no preference.		/// Return false if there is no preference.
virtual bool preferShiftsToClearExtremeBits(SDValue X) const {		virtual bool preferShiftsToClearExtremeBits(SDValue X) const {
// By default, let's assume that no one prefers shifts.		// By default, let's assume that no one prefers shifts.
return false;		return false;
}		}

		/// Should we tranform the IR-optimal check for whether given truncation
		/// down into KeptBits would be truncating or not:
		/// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
		/// Into it's more traditional form:
		/// ((%x << C) a>> C) dstcond %x
		/// Return true if we should transform.
		/// Return false if there is no preference.
		virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
		unsigned KeptBits) const {
		// By default, let's assume that no one prefers shifts.
		return false;
		}

/// Return true if the target wants to use the optimization that		/// Return true if the target wants to use the optimization that
/// turns ext(promotableInst1(...(promotableInstN(load)))) into		/// turns ext(promotableInst1(...(promotableInstN(load)))) into
/// promotedInst1(...(promotedInstN(ext(load)))).		/// promotedInst1(...(promotedInstN(ext(load)))).
bool enableExtLdPromotion() const { return EnableExtLdPromotion; }		bool enableExtLdPromotion() const { return EnableExtLdPromotion; }

/// Return true if the target can combine store(extractelement VectorTy,		/// Return true if the target can combine store(extractelement VectorTy,
/// Idx).		/// Idx).
/// \p Cost[out] gives the cost of that transformation when this is true.		/// \p Cost[out] gives the cost of that transformation when this is true.
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// fact that this can be implemented as a ctlz/srl pair, so that the dag		// fact that this can be implemented as a ctlz/srl pair, so that the dag
// combiner can fold the new nodes.		// combiner can fold the new nodes.
SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;		SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;

private:		private:
SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,		SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, DAGCombinerInfo &DCI,		ISD::CondCode Cond, DAGCombinerInfo &DCI,
const SDLoc &DL) const;		const SDLoc &DL) const;

		SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
		SDValue N1, ISD::CondCode Cond,
		DAGCombinerInfo &DCI,
		const SDLoc &DL) const;
};		};

/// Given an LLVM IR type and return type attributes, compute the return value		/// Given an LLVM IR type and return type attributes, compute the return value
/// EVTs and flags, and optionally also the offsets, if the return value is		/// EVTs and flags, and optionally also the offsets, if the return value is
/// being lowered to memory.		/// being lowered to memory.
void GetReturnInfo(Type *ReturnType, AttributeList attr,		void GetReturnInfo(Type *ReturnType, AttributeList attr,
SmallVectorImpl<ISD::OutputArg> &Outs,		SmallVectorImpl<ISD::OutputArg> &Outs,
const TargetLowering &TLI, const DataLayout &DL);		const TargetLowering &TLI, const DataLayout &DL);

} // end namespace llvm		} // end namespace llvm

#endif // LLVM_CODEGEN_TARGETLOWERING_H		#endif // LLVM_CODEGEN_TARGETLOWERING_H