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# llvm/trunk/test/CodeGen/RISCV/atomic-load-store.ll

1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||||
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2 | ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ | ||||

3 | ; RUN: | FileCheck -check-prefix=RV32I %s | ||||

4 | | ||||

5 | define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { | ||||

6 | ; RV32I-LABEL: atomic_load_i8_unordered: | ||||

7 | ; RV32I: # %bb.0: | ||||

8 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

9 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

10 | ; RV32I-NEXT: mv a1, zero | ||||

11 | ; RV32I-NEXT: call __atomic_load_1 | ||||

12 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

13 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

14 | ; RV32I-NEXT: ret | ||||

15 | %1 = load atomic i8, i8* %a unordered, align 1 | ||||

16 | ret i8 %1 | ||||

17 | } | ||||

18 | | ||||

19 | define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { | ||||

20 | ; RV32I-LABEL: atomic_load_i8_monotonic: | ||||

21 | ; RV32I: # %bb.0: | ||||

22 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

23 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

24 | ; RV32I-NEXT: mv a1, zero | ||||

25 | ; RV32I-NEXT: call __atomic_load_1 | ||||

26 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

27 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

28 | ; RV32I-NEXT: ret | ||||

29 | %1 = load atomic i8, i8* %a monotonic, align 1 | ||||

30 | ret i8 %1 | ||||

31 | } | ||||

32 | | ||||

33 | define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { | ||||

34 | ; RV32I-LABEL: atomic_load_i8_acquire: | ||||

35 | ; RV32I: # %bb.0: | ||||

36 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

37 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

38 | ; RV32I-NEXT: addi a1, zero, 2 | ||||

39 | ; RV32I-NEXT: call __atomic_load_1 | ||||

40 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

41 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

42 | ; RV32I-NEXT: ret | ||||

43 | %1 = load atomic i8, i8* %a acquire, align 1 | ||||

44 | ret i8 %1 | ||||

45 | } | ||||

46 | | ||||

47 | define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { | ||||

48 | ; RV32I-LABEL: atomic_load_i8_seq_cst: | ||||

49 | ; RV32I: # %bb.0: | ||||

50 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

51 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

52 | ; RV32I-NEXT: addi a1, zero, 5 | ||||

53 | ; RV32I-NEXT: call __atomic_load_1 | ||||

54 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

55 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

56 | ; RV32I-NEXT: ret | ||||

57 | %1 = load atomic i8, i8* %a seq_cst, align 1 | ||||

58 | ret i8 %1 | ||||

59 | } | ||||

60 | | ||||

61 | define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { | ||||

62 | ; RV32I-LABEL: atomic_load_i16_unordered: | ||||

63 | ; RV32I: # %bb.0: | ||||

64 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

65 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

66 | ; RV32I-NEXT: mv a1, zero | ||||

67 | ; RV32I-NEXT: call __atomic_load_2 | ||||

68 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

69 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

70 | ; RV32I-NEXT: ret | ||||

71 | %1 = load atomic i16, i16* %a unordered, align 2 | ||||

72 | ret i16 %1 | ||||

73 | } | ||||

74 | | ||||

75 | define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { | ||||

76 | ; RV32I-LABEL: atomic_load_i16_monotonic: | ||||

77 | ; RV32I: # %bb.0: | ||||

78 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

79 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

80 | ; RV32I-NEXT: mv a1, zero | ||||

81 | ; RV32I-NEXT: call __atomic_load_2 | ||||

82 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

83 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

84 | ; RV32I-NEXT: ret | ||||

85 | %1 = load atomic i16, i16* %a monotonic, align 2 | ||||

86 | ret i16 %1 | ||||

87 | } | ||||

88 | | ||||

89 | define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { | ||||

90 | ; RV32I-LABEL: atomic_load_i16_acquire: | ||||

91 | ; RV32I: # %bb.0: | ||||

92 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

93 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

94 | ; RV32I-NEXT: addi a1, zero, 2 | ||||

95 | ; RV32I-NEXT: call __atomic_load_2 | ||||

96 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

97 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

98 | ; RV32I-NEXT: ret | ||||

99 | %1 = load atomic i16, i16* %a acquire, align 2 | ||||

100 | ret i16 %1 | ||||

101 | } | ||||

102 | | ||||

103 | define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { | ||||

104 | ; RV32I-LABEL: atomic_load_i16_seq_cst: | ||||

105 | ; RV32I: # %bb.0: | ||||

106 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

107 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

108 | ; RV32I-NEXT: addi a1, zero, 5 | ||||

109 | ; RV32I-NEXT: call __atomic_load_2 | ||||

110 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

111 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

112 | ; RV32I-NEXT: ret | ||||

113 | %1 = load atomic i16, i16* %a seq_cst, align 2 | ||||

114 | ret i16 %1 | ||||

115 | } | ||||

116 | | ||||

117 | define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { | ||||

118 | ; RV32I-LABEL: atomic_load_i32_unordered: | ||||

119 | ; RV32I: # %bb.0: | ||||

120 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

121 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

122 | ; RV32I-NEXT: mv a1, zero | ||||

123 | ; RV32I-NEXT: call __atomic_load_4 | ||||

124 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

125 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

126 | ; RV32I-NEXT: ret | ||||

127 | %1 = load atomic i32, i32* %a unordered, align 4 | ||||

128 | ret i32 %1 | ||||

129 | } | ||||

130 | | ||||

131 | define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { | ||||

132 | ; RV32I-LABEL: atomic_load_i32_monotonic: | ||||

133 | ; RV32I: # %bb.0: | ||||

134 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

135 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

136 | ; RV32I-NEXT: mv a1, zero | ||||

137 | ; RV32I-NEXT: call __atomic_load_4 | ||||

138 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

139 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

140 | ; RV32I-NEXT: ret | ||||

141 | %1 = load atomic i32, i32* %a monotonic, align 4 | ||||

142 | ret i32 %1 | ||||

143 | } | ||||

144 | | ||||

145 | define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { | ||||

146 | ; RV32I-LABEL: atomic_load_i32_acquire: | ||||

147 | ; RV32I: # %bb.0: | ||||

148 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

149 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

150 | ; RV32I-NEXT: addi a1, zero, 2 | ||||

151 | ; RV32I-NEXT: call __atomic_load_4 | ||||

152 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

153 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

154 | ; RV32I-NEXT: ret | ||||

155 | %1 = load atomic i32, i32* %a acquire, align 4 | ||||

156 | ret i32 %1 | ||||

157 | } | ||||

158 | | ||||

159 | define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { | ||||

160 | ; RV32I-LABEL: atomic_load_i32_seq_cst: | ||||

161 | ; RV32I: # %bb.0: | ||||

162 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

163 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

164 | ; RV32I-NEXT: addi a1, zero, 5 | ||||

165 | ; RV32I-NEXT: call __atomic_load_4 | ||||

166 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

167 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

168 | ; RV32I-NEXT: ret | ||||

169 | %1 = load atomic i32, i32* %a seq_cst, align 4 | ||||

170 | ret i32 %1 | ||||

171 | } | ||||

172 | | ||||

173 | define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { | ||||

174 | ; RV32I-LABEL: atomic_load_i64_unordered: | ||||

175 | ; RV32I: # %bb.0: | ||||

176 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

177 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

178 | ; RV32I-NEXT: mv a1, zero | ||||

179 | ; RV32I-NEXT: call __atomic_load_8 | ||||

180 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

181 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

182 | ; RV32I-NEXT: ret | ||||

183 | %1 = load atomic i64, i64* %a unordered, align 8 | ||||

184 | ret i64 %1 | ||||

185 | } | ||||

186 | | ||||

187 | define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { | ||||

188 | ; RV32I-LABEL: atomic_load_i64_monotonic: | ||||

189 | ; RV32I: # %bb.0: | ||||

190 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

191 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

192 | ; RV32I-NEXT: mv a1, zero | ||||

193 | ; RV32I-NEXT: call __atomic_load_8 | ||||

194 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

195 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

196 | ; RV32I-NEXT: ret | ||||

197 | %1 = load atomic i64, i64* %a monotonic, align 8 | ||||

198 | ret i64 %1 | ||||

199 | } | ||||

200 | | ||||

201 | define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { | ||||

202 | ; RV32I-LABEL: atomic_load_i64_acquire: | ||||

203 | ; RV32I: # %bb.0: | ||||

204 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

205 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

206 | ; RV32I-NEXT: addi a1, zero, 2 | ||||

207 | ; RV32I-NEXT: call __atomic_load_8 | ||||

208 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

209 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

210 | ; RV32I-NEXT: ret | ||||

211 | %1 = load atomic i64, i64* %a acquire, align 8 | ||||

212 | ret i64 %1 | ||||

213 | } | ||||

214 | | ||||

215 | define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { | ||||

216 | ; RV32I-LABEL: atomic_load_i64_seq_cst: | ||||

217 | ; RV32I: # %bb.0: | ||||

218 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

219 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

220 | ; RV32I-NEXT: addi a1, zero, 5 | ||||

221 | ; RV32I-NEXT: call __atomic_load_8 | ||||

222 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

223 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

224 | ; RV32I-NEXT: ret | ||||

225 | %1 = load atomic i64, i64* %a seq_cst, align 8 | ||||

226 | ret i64 %1 | ||||

227 | } | ||||

228 | | ||||

229 | define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { | ||||

230 | ; RV32I-LABEL: atomic_store_i8_unordered: | ||||

231 | ; RV32I: # %bb.0: | ||||

232 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

233 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

234 | ; RV32I-NEXT: mv a2, zero | ||||

235 | ; RV32I-NEXT: call __atomic_store_1 | ||||

236 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

237 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

238 | ; RV32I-NEXT: ret | ||||

239 | store atomic i8 %b, i8* %a unordered, align 1 | ||||

240 | ret void | ||||

241 | } | ||||

242 | | ||||

243 | define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { | ||||

244 | ; RV32I-LABEL: atomic_store_i8_monotonic: | ||||

245 | ; RV32I: # %bb.0: | ||||

246 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

247 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

248 | ; RV32I-NEXT: mv a2, zero | ||||

249 | ; RV32I-NEXT: call __atomic_store_1 | ||||

250 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

251 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

252 | ; RV32I-NEXT: ret | ||||

253 | store atomic i8 %b, i8* %a monotonic, align 1 | ||||

254 | ret void | ||||

255 | } | ||||

256 | | ||||

257 | define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { | ||||

258 | ; RV32I-LABEL: atomic_store_i8_release: | ||||

259 | ; RV32I: # %bb.0: | ||||

260 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

261 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

262 | ; RV32I-NEXT: addi a2, zero, 3 | ||||

263 | ; RV32I-NEXT: call __atomic_store_1 | ||||

264 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

265 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

266 | ; RV32I-NEXT: ret | ||||

267 | store atomic i8 %b, i8* %a release, align 1 | ||||

268 | ret void | ||||

269 | } | ||||

270 | | ||||

271 | define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { | ||||

272 | ; RV32I-LABEL: atomic_store_i8_seq_cst: | ||||

273 | ; RV32I: # %bb.0: | ||||

274 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

275 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

276 | ; RV32I-NEXT: addi a2, zero, 5 | ||||

277 | ; RV32I-NEXT: call __atomic_store_1 | ||||

278 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

279 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

280 | ; RV32I-NEXT: ret | ||||

281 | store atomic i8 %b, i8* %a seq_cst, align 1 | ||||

282 | ret void | ||||

283 | } | ||||

284 | | ||||

285 | define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { | ||||

286 | ; RV32I-LABEL: atomic_store_i16_unordered: | ||||

287 | ; RV32I: # %bb.0: | ||||

288 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

289 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

290 | ; RV32I-NEXT: mv a2, zero | ||||

291 | ; RV32I-NEXT: call __atomic_store_2 | ||||

292 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

293 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

294 | ; RV32I-NEXT: ret | ||||

295 | store atomic i16 %b, i16* %a unordered, align 2 | ||||

296 | ret void | ||||

297 | } | ||||

298 | | ||||

299 | define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { | ||||

300 | ; RV32I-LABEL: atomic_store_i16_monotonic: | ||||

301 | ; RV32I: # %bb.0: | ||||

302 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

303 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

304 | ; RV32I-NEXT: mv a2, zero | ||||

305 | ; RV32I-NEXT: call __atomic_store_2 | ||||

306 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

307 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

308 | ; RV32I-NEXT: ret | ||||

309 | store atomic i16 %b, i16* %a monotonic, align 2 | ||||

310 | ret void | ||||

311 | } | ||||

312 | | ||||

313 | define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { | ||||

314 | ; RV32I-LABEL: atomic_store_i16_release: | ||||

315 | ; RV32I: # %bb.0: | ||||

316 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

317 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

318 | ; RV32I-NEXT: addi a2, zero, 3 | ||||

319 | ; RV32I-NEXT: call __atomic_store_2 | ||||

320 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

321 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

322 | ; RV32I-NEXT: ret | ||||

323 | store atomic i16 %b, i16* %a release, align 2 | ||||

324 | ret void | ||||

325 | } | ||||

326 | | ||||

327 | define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { | ||||

328 | ; RV32I-LABEL: atomic_store_i16_seq_cst: | ||||

329 | ; RV32I: # %bb.0: | ||||

330 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

331 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

332 | ; RV32I-NEXT: addi a2, zero, 5 | ||||

333 | ; RV32I-NEXT: call __atomic_store_2 | ||||

334 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

335 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

336 | ; RV32I-NEXT: ret | ||||

337 | store atomic i16 %b, i16* %a seq_cst, align 2 | ||||

338 | ret void | ||||

339 | } | ||||

340 | | ||||

341 | define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { | ||||

342 | ; RV32I-LABEL: atomic_store_i32_unordered: | ||||

343 | ; RV32I: # %bb.0: | ||||

344 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

345 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

346 | ; RV32I-NEXT: mv a2, zero | ||||

347 | ; RV32I-NEXT: call __atomic_store_4 | ||||

348 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

349 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

350 | ; RV32I-NEXT: ret | ||||

351 | store atomic i32 %b, i32* %a unordered, align 4 | ||||

352 | ret void | ||||

353 | } | ||||

354 | | ||||

355 | define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { | ||||

356 | ; RV32I-LABEL: atomic_store_i32_monotonic: | ||||

357 | ; RV32I: # %bb.0: | ||||

358 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

359 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

360 | ; RV32I-NEXT: mv a2, zero | ||||

361 | ; RV32I-NEXT: call __atomic_store_4 | ||||

362 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

363 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

364 | ; RV32I-NEXT: ret | ||||

365 | store atomic i32 %b, i32* %a monotonic, align 4 | ||||

366 | ret void | ||||

367 | } | ||||

368 | | ||||

369 | define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { | ||||

370 | ; RV32I-LABEL: atomic_store_i32_release: | ||||

371 | ; RV32I: # %bb.0: | ||||

372 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

373 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

374 | ; RV32I-NEXT: addi a2, zero, 3 | ||||

375 | ; RV32I-NEXT: call __atomic_store_4 | ||||

376 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

377 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

378 | ; RV32I-NEXT: ret | ||||

379 | store atomic i32 %b, i32* %a release, align 4 | ||||

380 | ret void | ||||

381 | } | ||||

382 | | ||||

383 | define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { | ||||

384 | ; RV32I-LABEL: atomic_store_i32_seq_cst: | ||||

385 | ; RV32I: # %bb.0: | ||||

386 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

387 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

388 | ; RV32I-NEXT: addi a2, zero, 5 | ||||

389 | ; RV32I-NEXT: call __atomic_store_4 | ||||

390 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

391 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

392 | ; RV32I-NEXT: ret | ||||

393 | store atomic i32 %b, i32* %a seq_cst, align 4 | ||||

394 | ret void | ||||

395 | } | ||||

396 | | ||||

397 | define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind { | ||||

398 | ; RV32I-LABEL: atomic_store_i64_unordered: | ||||

399 | ; RV32I: # %bb.0: | ||||

400 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

401 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

402 | ; RV32I-NEXT: mv a3, zero | ||||

403 | ; RV32I-NEXT: call __atomic_store_8 | ||||

404 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

405 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

406 | ; RV32I-NEXT: ret | ||||

407 | store atomic i64 %b, i64* %a unordered, align 8 | ||||

408 | ret void | ||||

409 | } | ||||

410 | | ||||

411 | define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind { | ||||

412 | ; RV32I-LABEL: atomic_store_i64_monotonic: | ||||

413 | ; RV32I: # %bb.0: | ||||

414 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

415 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

416 | ; RV32I-NEXT: mv a3, zero | ||||

417 | ; RV32I-NEXT: call __atomic_store_8 | ||||

418 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

419 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

420 | ; RV32I-NEXT: ret | ||||

421 | store atomic i64 %b, i64* %a monotonic, align 8 | ||||

422 | ret void | ||||

423 | } | ||||

424 | | ||||

425 | define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind { | ||||

426 | ; RV32I-LABEL: atomic_store_i64_release: | ||||

427 | ; RV32I: # %bb.0: | ||||

428 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

429 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

430 | ; RV32I-NEXT: addi a3, zero, 3 | ||||

431 | ; RV32I-NEXT: call __atomic_store_8 | ||||

432 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

433 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

434 | ; RV32I-NEXT: ret | ||||

435 | store atomic i64 %b, i64* %a release, align 8 | ||||

436 | ret void | ||||

437 | } | ||||

438 | | ||||

439 | define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind { | ||||

440 | ; RV32I-LABEL: atomic_store_i64_seq_cst: | ||||

441 | ; RV32I: # %bb.0: | ||||

442 | ; RV32I-NEXT: addi sp, sp, -16 | ||||

443 | ; RV32I-NEXT: sw ra, 12(sp) | ||||

444 | ; RV32I-NEXT: addi a3, zero, 5 | ||||

445 | ; RV32I-NEXT: call __atomic_store_8 | ||||

446 | ; RV32I-NEXT: lw ra, 12(sp) | ||||

447 | ; RV32I-NEXT: addi sp, sp, 16 | ||||

448 | ; RV32I-NEXT: ret | ||||

449 | store atomic i64 %b, i64* %a seq_cst, align 8 | ||||

450 | ret void | ||||

451 | } |