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lib/Target/AArch64/AArch64ISelLowering.cpp
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Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Lines | if (Subtarget->hasNEON()) { | ||||
addQRTypeForNEON(MVT::v2f64); | addQRTypeForNEON(MVT::v2f64); | ||||
addQRTypeForNEON(MVT::v16i8); | addQRTypeForNEON(MVT::v16i8); | ||||
addQRTypeForNEON(MVT::v8i16); | addQRTypeForNEON(MVT::v8i16); | ||||
addQRTypeForNEON(MVT::v4i32); | addQRTypeForNEON(MVT::v4i32); | ||||
addQRTypeForNEON(MVT::v2i64); | addQRTypeForNEON(MVT::v2i64); | ||||
addQRTypeForNEON(MVT::v8f16); | addQRTypeForNEON(MVT::v8f16); | ||||
} | } | ||||
if (Subtarget->hasSVE()) { | |||||
// Add legal sve predicate types | |||||
addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass); | |||||
addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass); | |||||
addRegisterClass(MVT::nxv8i1, &AArch64::PPRRegClass); | |||||
addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass); | |||||
// Add legal sve data types | |||||
addRegisterClass(MVT::nxv16i8, &AArch64::ZPRRegClass); | |||||
addRegisterClass(MVT::nxv8i16, &AArch64::ZPRRegClass); | |||||
addRegisterClass(MVT::nxv4i32, &AArch64::ZPRRegClass); | |||||
addRegisterClass(MVT::nxv2i64, &AArch64::ZPRRegClass); | |||||
} | |||||
// Compute derived properties from the register classes | // Compute derived properties from the register classes | ||||
computeRegisterProperties(Subtarget->getRegisterInfo()); | computeRegisterProperties(Subtarget->getRegisterInfo()); | ||||
// Provide all sorts of operation actions | // Provide all sorts of operation actions | ||||
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); | setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); | ||||
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); | setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); | ||||
setOperationAction(ISD::SETCC, MVT::i32, Custom); | setOperationAction(ISD::SETCC, MVT::i32, Custom); | ||||
setOperationAction(ISD::SETCC, MVT::i64, Custom); | setOperationAction(ISD::SETCC, MVT::i64, Custom); | ||||
▲ Show 20 Lines • Show All 2,725 Lines • ▼ Show 20 Lines | if (VA.isRegLoc()) { | ||||
else if (RegVT == MVT::f16) | else if (RegVT == MVT::f16) | ||||
RC = &AArch64::FPR16RegClass; | RC = &AArch64::FPR16RegClass; | ||||
else if (RegVT == MVT::f32) | else if (RegVT == MVT::f32) | ||||
RC = &AArch64::FPR32RegClass; | RC = &AArch64::FPR32RegClass; | ||||
else if (RegVT == MVT::f64 || RegVT.is64BitVector()) | else if (RegVT == MVT::f64 || RegVT.is64BitVector()) | ||||
RC = &AArch64::FPR64RegClass; | RC = &AArch64::FPR64RegClass; | ||||
else if (RegVT == MVT::f128 || RegVT.is128BitVector()) | else if (RegVT == MVT::f128 || RegVT.is128BitVector()) | ||||
RC = &AArch64::FPR128RegClass; | RC = &AArch64::FPR128RegClass; | ||||
else if (RegVT.isScalableVector() && | |||||
RegVT.getVectorElementType() == MVT::i1) | |||||
RC = &AArch64::PPRRegClass; | |||||
else if (RegVT.isScalableVector()) | |||||
RC = &AArch64::ZPRRegClass; | |||||
else | else | ||||
llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); | llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); | ||||
// Transform the arguments in physical registers into virtual ones. | // Transform the arguments in physical registers into virtual ones. | ||||
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); | unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); | ||||
ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); | ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); | ||||
// If this is an 8, 16 or 32-bit value, it is really passed promoted | // If this is an 8, 16 or 32-bit value, it is really passed promoted | ||||
▲ Show 20 Lines • Show All 8,542 Lines • Show Last 20 Lines |