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Differential D47771 Diff 149952 lib/Target/AArch64/AArch64ISelLowering.cpp

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lib/Target/AArch64/AArch64ISelLowering.cpp

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Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Line(s)140 if (Subtarget->hasNEON()) {
153 addQRTypeForNEON(MVT::v2f64); 153​ addQRTypeForNEON(MVT::v2f64);
154 addQRTypeForNEON(MVT::v16i8); 154​ addQRTypeForNEON(MVT::v16i8);
155 addQRTypeForNEON(MVT::v8i16); 155​ addQRTypeForNEON(MVT::v8i16);
156 addQRTypeForNEON(MVT::v4i32); 156​ addQRTypeForNEON(MVT::v4i32);
157 addQRTypeForNEON(MVT::v2i64); 157​ addQRTypeForNEON(MVT::v2i64);
158 addQRTypeForNEON(MVT::v8f16); 158​ addQRTypeForNEON(MVT::v8f16);
159 } 159​ }
160 160​
161​ if (Subtarget->hasSVE()) {
162​ // Add legal sve predicate types
163​ addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass);
164​ addRegisterClass(MVT::nxv4i1, &AArch64::PPRRegClass);
165​ addRegisterClass(MVT::nxv8i1, &AArch64::PPRRegClass);
166​ addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass);
167​
168​ // Add legal sve data types
169​ addRegisterClass(MVT::nxv16i8, &AArch64::ZPRRegClass);
170​ addRegisterClass(MVT::nxv8i16, &AArch64::ZPRRegClass);
171​ addRegisterClass(MVT::nxv4i32, &AArch64::ZPRRegClass);
172​ addRegisterClass(MVT::nxv2i64, &AArch64::ZPRRegClass);
173​ }
174​
161 // Compute derived properties from the register classes 175​ // Compute derived properties from the register classes
162 computeRegisterProperties(Subtarget->getRegisterInfo()); 176​ computeRegisterProperties(Subtarget->getRegisterInfo());
163 177​
164 // Provide all sorts of operation actions 178​ // Provide all sorts of operation actions
165 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 179​ setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
166 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 180​ setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
167 setOperationAction(ISD::SETCC, MVT::i32, Custom); 181​ setOperationAction(ISD::SETCC, MVT::i32, Custom);
168 setOperationAction(ISD::SETCC, MVT::i64, Custom); 182​ setOperationAction(ISD::SETCC, MVT::i64, Custom);
▲ Show 20 Lines • Show All 2725 Lines • ▼ Show 20 Line(s)2897 if (VA.isRegLoc()) {
2894 else if (RegVT == MVT::f16) 2908​ else if (RegVT == MVT::f16)
2895 RC = &AArch64::FPR16RegClass; 2909​ RC = &AArch64::FPR16RegClass;
2896 else if (RegVT == MVT::f32) 2910​ else if (RegVT == MVT::f32)
2897 RC = &AArch64::FPR32RegClass; 2911​ RC = &AArch64::FPR32RegClass;
2898 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) 2912​ else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2899 RC = &AArch64::FPR64RegClass; 2913​ RC = &AArch64::FPR64RegClass;
2900 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) 2914​ else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2901 RC = &AArch64::FPR128RegClass; 2915​ RC = &AArch64::FPR128RegClass;
2916​ else if (RegVT.isScalableVector() &&
2917​ RegVT.getVectorElementType() == MVT::i1)
2918​ RC = &AArch64::PPRRegClass;
2919​ else if (RegVT.isScalableVector())
2920​ RC = &AArch64::ZPRRegClass;
2902 else 2921​ else
2903 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2922​ llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2904 2923​
2905 // Transform the arguments in physical registers into virtual ones. 2924​ // Transform the arguments in physical registers into virtual ones.
2906 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2925​ unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2907 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2926​ ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2908 2927​
2909 // If this is an 8, 16 or 32-bit value, it is really passed promoted 2928​ // If this is an 8, 16 or 32-bit value, it is really passed promoted
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