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lib/Target/AArch64/AArch64CallingConvention.td
| Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines | def CC_AArch64_AAPCS : CallingConv<[ | ||||
| CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], | CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], | ||||
| [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | ||||
| CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], | CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], | ||||
| CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], | CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], | ||||
| [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | ||||
| CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], | CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], | ||||
| CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | ||||
| CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv8f16, nxv4f32, nxv2f64], | |||||
| CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, | |||||
| CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], | |||||
| CCAssignToReg<[P0, P1, P2, P3]>>, | |||||
| // If more than will fit in registers, pass them on the stack instead. | // If more than will fit in registers, pass them on the stack instead. | ||||
| CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>, | CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>, | ||||
| CCIfType<[i32, f32], CCAssignToStack<8, 8>>, | CCIfType<[i32, f32], CCAssignToStack<8, 8>>, | ||||
| CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], | CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16], | ||||
| CCAssignToStack<8, 8>>, | CCAssignToStack<8, 8>>, | ||||
| CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], | CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], | ||||
| CCAssignToStack<16, 16>> | CCAssignToStack<16, 16>> | ||||
| ]>; | ]>; | ||||
| Show All 22 Lines | def RetCC_AArch64_AAPCS : CallingConv<[ | ||||
| CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], | CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7], | ||||
| [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | ||||
| CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], | CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], | ||||
| [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | ||||
| CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], | CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16], | ||||
| CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], | CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7], | ||||
| [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | ||||
| CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], | CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], | ||||
| CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>> | CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, | ||||
| CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv8f16, nxv4f32, nxv2f64], | |||||
| CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>, | |||||
| CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1], | |||||
| CCAssignToReg<[P0, P1, P2, P3]>> | |||||
| ]>; | ]>; | ||||
| // Vararg functions on windows pass floats in integer registers | // Vararg functions on windows pass floats in integer registers | ||||
| def CC_AArch64_Win64_VarArg : CallingConv<[ | def CC_AArch64_Win64_VarArg : CallingConv<[ | ||||
| CCIfType<[f16, f32], CCPromoteToType<f64>>, | CCIfType<[f16, f32], CCPromoteToType<f64>>, | ||||
| CCIfType<[f64], CCBitConvertToType<i64>>, | CCIfType<[f64], CCBitConvertToType<i64>>, | ||||
| CCDelegateTo<CC_AArch64_AAPCS> | CCDelegateTo<CC_AArch64_AAPCS> | ||||
| ]>; | ]>; | ||||
| ▲ Show 20 Lines • Show All 237 Lines • Show Last 20 Lines | |||||