Differential D47771 Diff 149952 lib/Target/AArch64/AArch64CallingConvention.td

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lib/Target/AArch64/AArch64CallingConvention.td

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Line(s)		25	def CC_AArch64_AAPCS : CallingConv<[
75	CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],	75		CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
76	[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,	76		[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
77	CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],	77		CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
78	CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],	78		CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
79	[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,	79		[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
80	CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],	80		CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
81	CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,	81		CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
82		82
		83		CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv8f16, nxv4f32, nxv2f64],
		84		CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
		85		CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1],
		86		CCAssignToReg<[P0, P1, P2, P3]>>,
		87
83	// If more than will fit in registers, pass them on the stack instead.	88		// If more than will fit in registers, pass them on the stack instead.
84	CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>,	89		CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>,
85	CCIfType<[i32, f32], CCAssignToStack<8, 8>>,	90		CCIfType<[i32, f32], CCAssignToStack<8, 8>>,
86	CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],	91		CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
87	CCAssignToStack<8, 8>>,	92		CCAssignToStack<8, 8>>,
88	CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],	93		CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
89	CCAssignToStack<16, 16>>	94		CCAssignToStack<16, 16>>
90	]>;	95		]>;
Show All 22 Lines		97	def RetCC_AArch64_AAPCS : CallingConv<[
113	CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],	118		CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
114	[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,	119		[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
115	CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],	120		CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
116	[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,	121		[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
117	CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],	122		CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
118	CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],	123		CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
119	[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,	124		[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
120	CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],	125		CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
121	CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>	126		CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
		127
		128		CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv8f16, nxv4f32, nxv2f64],
		129		CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
		130
		131		CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1],
		132		CCAssignToReg<[P0, P1, P2, P3]>>
122	]>;	133		]>;
123		134
124	// Vararg functions on windows pass floats in integer registers	135		// Vararg functions on windows pass floats in integer registers
125	def CC_AArch64_Win64_VarArg : CallingConv<[	136		def CC_AArch64_Win64_VarArg : CallingConv<[
126	CCIfType<[f16, f32], CCPromoteToType<f64>>,	137		CCIfType<[f16, f32], CCPromoteToType<f64>>,
127	CCIfType<[f64], CCBitConvertToType<i64>>,	138		CCIfType<[f64], CCBitConvertToType<i64>>,
128	CCDelegateTo<CC_AArch64_AAPCS>	139		CCDelegateTo<CC_AArch64_AAPCS>
129	]>;	140		]>;
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