Differential D45395 Diff 148275 lib/Target/RISCV/RISCVRegisterInfo.td

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lib/Target/RISCV/RISCVRegisterInfo.td

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines	def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
(sequence "X%u", 10, 15),		(sequence "X%u", 10, 15),
(sequence "X%u", 8, 9)		(sequence "X%u", 8, 9)
)> {		)> {
let RegInfos = RegInfoByHwMode<		let RegInfos = RegInfoByHwMode<
[RV32, RV64, DefaultMode],		[RV32, RV64, DefaultMode],
[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;		[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
}		}

		// For indirect tail calls, we can't use callee-saved registers, as they are
		// restored to the saved value before the tail call, which would clobber a call
		// address.
		def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
		mgrangAuthorUnsubmitted Not Done Reply Inline Actions Can we also use x28-x31 (Caller temporaries) here? mgrang: Can we also use x28-x31 (Caller temporaries) here?
		HsiangKaiUnsubmitted Not Done Reply Inline Actions Could we also use x10-x17 (Argument registers)? I think we could let RA use any registers except callee-saved registers and x0-x4. We could not use callee-saved registers, because these registers will be restored before tailcall and the address register will be clobbered. We could not use x0-x4, because these registers have special meaning in RISCV architecture. HsiangKai: Could we also use x10-x17 (Argument registers)? I think we could let RA use any registers…
		asbUnsubmitted Not Done Reply Inline Actions I agree with @HsiangKai, it seems as though any register that isn't callee-saved (or otherwise has a special meaning) should be safe to use. Or at least, all such registers will avoid the problem described in the comment. asb: I agree with @HsiangKai, it seems as though any register that isn't callee-saved (or otherwise…
		(sequence "X%u", 5, 7),
		(sequence "X%u", 10, 17),
		(sequence "X%u", 28, 31)
		)> {
		let RegInfos = RegInfoByHwMode<
		[RV32, RV64, DefaultMode],
		[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
		}

def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {		def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
let RegInfos = RegInfoByHwMode<		let RegInfos = RegInfoByHwMode<
[RV32, RV64, DefaultMode],		[RV32, RV64, DefaultMode],
[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;		[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
}		}

// Floating point registers		// Floating point registers
let RegAltNameIndices = [ABIRegAltName] in {		let RegAltNameIndices = [ABIRegAltName] in {
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