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Differential D4957 Diff 13381 lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

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lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

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void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize, void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
unsigned ReturnReg) {} unsigned ReturnReg) {}
void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {} void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) { void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
} }
void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) { void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
forbidModuleDirective(); forbidModuleDirective();
} }
void MipsTargetStreamer::emitDirectiveSetMips0() {}
void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines OS << "\t.frame\t$"
<< StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n'; << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
} }
void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) { void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
OS << "\t.set arch=" << Arch << "\n"; OS << "\t.set arch=" << Arch << "\n";
MipsTargetStreamer::emitDirectiveSetArch(Arch); MipsTargetStreamer::emitDirectiveSetArch(Arch);
} }
void MipsTargetAsmStreamer::emitDirectiveSetMips0() { OS << "\t.set\tmips0\n"; }
void MipsTargetAsmStreamer::emitDirectiveSetMips1() { void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
OS << "\t.set\tmips1\n"; OS << "\t.set\tmips1\n";
MipsTargetStreamer::emitDirectiveSetMips1(); MipsTargetStreamer::emitDirectiveSetMips1();
} }
void MipsTargetAsmStreamer::emitDirectiveSetMips2() { void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
OS << "\t.set\tmips2\n"; OS << "\t.set\tmips2\n";
MipsTargetStreamer::emitDirectiveSetMips2(); MipsTargetStreamer::emitDirectiveSetMips2();
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