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llvm/trunk/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
| Show First 20 Lines • Show All 389 Lines • ▼ Show 20 Lines | void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, | ||||
| MachineOperand &LoadBase = getBaseOperand(LoadInst); | MachineOperand &LoadBase = getBaseOperand(LoadInst); | ||||
| MachineOperand &StoreBase = getBaseOperand(StoreInst); | MachineOperand &StoreBase = getBaseOperand(StoreInst); | ||||
| MachineBasicBlock *MBB = LoadInst->getParent(); | MachineBasicBlock *MBB = LoadInst->getParent(); | ||||
| MachineMemOperand *LMMO = *LoadInst->memoperands_begin(); | MachineMemOperand *LMMO = *LoadInst->memoperands_begin(); | ||||
| MachineMemOperand *SMMO = *StoreInst->memoperands_begin(); | MachineMemOperand *SMMO = *StoreInst->memoperands_begin(); | ||||
| unsigned Reg1 = MRI->createVirtualRegister( | unsigned Reg1 = MRI->createVirtualRegister( | ||||
| TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent()))); | TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent()))); | ||||
| BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode), Reg1) | MachineInstr *NewLoad = | ||||
| BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode), | |||||
| Reg1) | |||||
| .add(LoadBase) | .add(LoadBase) | ||||
| .addImm(1) | .addImm(1) | ||||
| .addReg(X86::NoRegister) | .addReg(X86::NoRegister) | ||||
| .addImm(LoadDisp) | .addImm(LoadDisp) | ||||
| .addReg(X86::NoRegister) | .addReg(X86::NoRegister) | ||||
| .addMemOperand( | .addMemOperand( | ||||
| MBB->getParent()->getMachineMemOperand(LMMO, LMMOffset, Size)); | MBB->getParent()->getMachineMemOperand(LMMO, LMMOffset, Size)); | ||||
| DEBUG(LoadInst->getPrevNode()->dump()); | if (LoadBase.isReg()) | ||||
| getBaseOperand(NewLoad).setIsKill(false); | |||||
| DEBUG(NewLoad->dump()); | |||||
| // If the load and store are consecutive, use the loadInst location to | // If the load and store are consecutive, use the loadInst location to | ||||
| // reduce register pressure. | // reduce register pressure. | ||||
| MachineInstr *StInst = StoreInst; | MachineInstr *StInst = StoreInst; | ||||
| if (StoreInst->getPrevNode() == LoadInst) | if (StoreInst->getPrevNode() == LoadInst) | ||||
| StInst = LoadInst; | StInst = LoadInst; | ||||
| MachineInstr *NewStore = | |||||
| BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode)) | BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode)) | ||||
| .add(StoreBase) | .add(StoreBase) | ||||
| .addImm(1) | .addImm(1) | ||||
| .addReg(X86::NoRegister) | .addReg(X86::NoRegister) | ||||
| .addImm(StoreDisp) | .addImm(StoreDisp) | ||||
| .addReg(X86::NoRegister) | .addReg(X86::NoRegister) | ||||
| .addReg(Reg1) | .addReg(Reg1) | ||||
| .addMemOperand( | .addMemOperand( | ||||
| MBB->getParent()->getMachineMemOperand(SMMO, SMMOffset, Size)); | MBB->getParent()->getMachineMemOperand(SMMO, SMMOffset, Size)); | ||||
| DEBUG(StInst->getPrevNode()->dump()); | if (StoreBase.isReg()) | ||||
| getBaseOperand(NewStore).setIsKill(false); | |||||
| MachineOperand &StoreSrcVReg = StoreInst->getOperand(X86::AddrNumOperands); | |||||
| assert(StoreSrcVReg.isReg() && "Expected virtual register"); | |||||
| NewStore->getOperand(X86::AddrNumOperands).setIsKill(StoreSrcVReg.isKill()); | |||||
| DEBUG(NewStore->dump()); | |||||
| } | } | ||||
| void X86AvoidSFBPass::buildCopies(int Size, MachineInstr *LoadInst, | void X86AvoidSFBPass::buildCopies(int Size, MachineInstr *LoadInst, | ||||
| int64_t LdDispImm, MachineInstr *StoreInst, | int64_t LdDispImm, MachineInstr *StoreInst, | ||||
| int64_t StDispImm, int64_t LMMOffset, | int64_t StDispImm, int64_t LMMOffset, | ||||
| int64_t SMMOffset) { | int64_t SMMOffset) { | ||||
| int LdDisp = LdDispImm; | int LdDisp = LdDispImm; | ||||
| int StDisp = StDispImm; | int StDisp = StDispImm; | ||||
| ▲ Show 20 Lines • Show All 293 Lines • Show Last 20 Lines | |||||