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test/CodeGen/ARM/cortexr52-misched-basic.ll
| ; REQUIRES: asserts | ; REQUIRES: asserts | ||||
| ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED | ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED | ||||
| ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC | ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC | ||||
| ; | ; | ||||
| ; Check the latency for instructions for both generic and cortex-r52. | ; Check the latency for instructions for both generic and cortex-r52. | ||||
| ; Cortex-r52 machine model will cause the div to be sceduled before eor | ; Cortex-r52 machine model will cause the div to be sceduled before eor | ||||
| ; as div takes more cycles to compute than eor. | ; as div takes more cycles to compute than eor. | ||||
| ; | ; | ||||
| ; CHECK: ********** MI Scheduling ********** | ; CHECK: ********** MI Scheduling ********** | ||||
| ; CHECK: foo:%bb.0 entry | ; CHECK: foo:%bb.0 entry | ||||
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