Differential D45253 Diff 143354 llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

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llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

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Show First 20 Lines • Show All 21,387 Lines • ▼ Show 20 Lines	case llvm::Intrinsic::x86_flags_write_u64: {
// sequence.		// sequence.
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();		MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
MFI.setHasCopyImplyingStackAdjustment(true);		MFI.setHasCopyImplyingStackAdjustment(true);
// Don't do anything here, we will expand these intrinsics out later		// Don't do anything here, we will expand these intrinsics out later
// during ExpandISelPseudos in EmitInstrWithCustomInserter.		// during ExpandISelPseudos in EmitInstrWithCustomInserter.
return SDValue();		return SDValue();
}		}
case Intrinsic::x86_lwpins32:		case Intrinsic::x86_lwpins32:
case Intrinsic::x86_lwpins64: {		case Intrinsic::x86_lwpins64:
		case Intrinsic::x86_umwait:
		case Intrinsic::x86_tpause: {
SDLoc dl(Op);		SDLoc dl(Op);
SDValue Chain = Op->getOperand(0);		SDValue Chain = Op->getOperand(0);
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);		SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
SDValue LwpIns =		unsigned Opcode;
DAG.getNode(X86ISD::LWPINS, dl, VTs, Chain, Op->getOperand(2),
		switch (IntNo) {
		default: llvm_unreachable("Impossible intrinsic");
		case Intrinsic::x86_umwait:
		Opcode = X86ISD::UMWAIT;
		break;
		case Intrinsic::x86_tpause:
		Opcode = X86ISD::TPAUSE;
		break;
		case Intrinsic::x86_lwpins32:
		case Intrinsic::x86_lwpins64:
		Opcode = X86ISD::LWPINS;
		break;
		}

		SDValue Operation =
		DAG.getNode(Opcode, dl, VTs, Chain, Op->getOperand(2),
Op->getOperand(3), Op->getOperand(4));		Op->getOperand(3), Op->getOperand(4));
SDValue SetCC = getSETCC(X86::COND_B, LwpIns.getValue(0), dl, DAG);		SDValue SetCC = getSETCC(X86::COND_B, Operation.getValue(0), dl, DAG);
SDValue Result = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, SetCC);		SDValue Result = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, SetCC);
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result,		return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result,
LwpIns.getValue(1));		Operation.getValue(1));
}		}
}		}
return SDValue();		return SDValue();
}		}

SDLoc dl(Op);		SDLoc dl(Op);
switch(IntrData->Type) {		switch(IntrData->Type) {
default: llvm_unreachable("Unknown Intrinsic Type");		default: llvm_unreachable("Unknown Intrinsic Type");
▲ Show 20 Lines • Show All 4,426 Lines • ▼ Show 20 Lines	const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::VPDPWSSD: return "X86ISD::VPDPWSSD";		case X86ISD::VPDPWSSD: return "X86ISD::VPDPWSSD";
case X86ISD::VPDPWSSDS: return "X86ISD::VPDPWSSDS";		case X86ISD::VPDPWSSDS: return "X86ISD::VPDPWSSDS";
case X86ISD::VPSHUFBITQMB: return "X86ISD::VPSHUFBITQMB";		case X86ISD::VPSHUFBITQMB: return "X86ISD::VPSHUFBITQMB";
case X86ISD::GF2P8MULB: return "X86ISD::GF2P8MULB";		case X86ISD::GF2P8MULB: return "X86ISD::GF2P8MULB";
case X86ISD::GF2P8AFFINEQB: return "X86ISD::GF2P8AFFINEQB";		case X86ISD::GF2P8AFFINEQB: return "X86ISD::GF2P8AFFINEQB";
case X86ISD::GF2P8AFFINEINVQB: return "X86ISD::GF2P8AFFINEINVQB";		case X86ISD::GF2P8AFFINEINVQB: return "X86ISD::GF2P8AFFINEINVQB";
case X86ISD::NT_CALL: return "X86ISD::NT_CALL";		case X86ISD::NT_CALL: return "X86ISD::NT_CALL";
case X86ISD::NT_BRIND: return "X86ISD::NT_BRIND";		case X86ISD::NT_BRIND: return "X86ISD::NT_BRIND";
		case X86ISD::UMWAIT: return "X86ISD::UMWAIT";
		case X86ISD::TPAUSE: return "X86ISD::TPAUSE";
}		}
return nullptr;		return nullptr;
}		}

/// Return true if the addressing mode represented by AM is legal for this		/// Return true if the addressing mode represented by AM is legal for this
/// target, for a load/store of the specified type.		/// target, for a load/store of the specified type.
bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,		bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, Type *Ty,		const AddrMode &AM, Type *Ty,
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