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llvm/trunk/lib/Target/X86/X86InstrInfo.td
| Show First 20 Lines • Show All 301 Lines • ▼ Show 20 Lines | |||||
| def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, | def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, | ||||
| [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; | [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; | ||||
| def X86lwpins : SDNode<"X86ISD::LWPINS", | def X86lwpins : SDNode<"X86ISD::LWPINS", | ||||
| SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, | SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, | ||||
| SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, | SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, | ||||
| [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; | [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; | ||||
| def X86umwait : SDNode<"X86ISD::UMWAIT", | |||||
| SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, | |||||
| SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, | |||||
| [SDNPHasChain, SDNPSideEffect]>; | |||||
| def X86tpause : SDNode<"X86ISD::TPAUSE", | |||||
| SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, | |||||
| SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, | |||||
| [SDNPHasChain, SDNPSideEffect]>; | |||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // X86 Operand Definitions. | // X86 Operand Definitions. | ||||
| // | // | ||||
| // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for | // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for | ||||
| // the index operand of an address, to conform to x86 encoding restrictions. | // the index operand of an address, to conform to x86 encoding restrictions. | ||||
| def ptr_rc_nosp : PointerLikeRegClass<1>; | def ptr_rc_nosp : PointerLikeRegClass<1>; | ||||
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| def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; | ||||
| def HasMPX : Predicate<"Subtarget->hasMPX()">; | def HasMPX : Predicate<"Subtarget->hasMPX()">; | ||||
| def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; | def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; | ||||
| def HasIBT : Predicate<"Subtarget->hasIBT()">; | def HasIBT : Predicate<"Subtarget->hasIBT()">; | ||||
| def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; | def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; | ||||
| def HasCLWB : Predicate<"Subtarget->hasCLWB()">; | def HasCLWB : Predicate<"Subtarget->hasCLWB()">; | ||||
| def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; | def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; | ||||
| def HasRDPID : Predicate<"Subtarget->hasRDPID()">; | def HasRDPID : Predicate<"Subtarget->hasRDPID()">; | ||||
| def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; | |||||
| def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; | def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; | ||||
| def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, | def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, | ||||
| AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; | AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; | ||||
| def In64BitMode : Predicate<"Subtarget->is64Bit()">, | def In64BitMode : Predicate<"Subtarget->is64Bit()">, | ||||
| AssemblerPredicate<"Mode64Bit", "64-bit mode">; | AssemblerPredicate<"Mode64Bit", "64-bit mode">; | ||||
| def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; | def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; | ||||
| def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; | def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; | ||||
| def In16BitMode : Predicate<"Subtarget->is16Bit()">, | def In16BitMode : Predicate<"Subtarget->is16Bit()">, | ||||
| ▲ Show 20 Lines • Show All 1,733 Lines • ▼ Show 20 Lines | def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, | ||||
| Requires<[ In64BitMode ]>; | Requires<[ In64BitMode ]>; | ||||
| def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, | def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORXrrr)>, | ||||
| Requires<[ Not64BitMode ]>; | Requires<[ Not64BitMode ]>; | ||||
| def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, | def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORXrrr)>, | ||||
| Requires<[ In64BitMode ]>; | Requires<[ In64BitMode ]>; | ||||
| //===----------------------------------------------------------------------===// | //===----------------------------------------------------------------------===// | ||||
| // WAITPKG Instructions | |||||
| // | |||||
| let SchedRW = [WriteSystem] in { | |||||
| def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), | |||||
| "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, | |||||
| XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; | |||||
| def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), | |||||
| "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, | |||||
| XS, AdSize32, Requires<[HasWAITPKG]>; | |||||
| def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), | |||||
| "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, | |||||
| XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; | |||||
| let Uses = [EAX, EDX], Defs = [EFLAGS] in { | |||||
| def UMWAIT : I<0xAE, MRM6r, | |||||
| (outs), (ins GR32orGR64:$src), "umwait\t$src", | |||||
| [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, | |||||
| XD, Requires<[HasWAITPKG]>; | |||||
| def TPAUSE : I<0xAE, MRM6r, | |||||
| (outs), (ins GR32orGR64:$src), "tpause\t$src", | |||||
| [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, | |||||
| PD, Requires<[HasWAITPKG]>; | |||||
| } | |||||
| } // SchedRW | |||||
| //===----------------------------------------------------------------------===// | |||||
| // CLZERO Instruction | // CLZERO Instruction | ||||
| // | // | ||||
| let SchedRW = [WriteSystem] in { | let SchedRW = [WriteSystem] in { | ||||
| let Uses = [EAX] in | let Uses = [EAX] in | ||||
| def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, | def CLZEROr : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, | ||||
| TB, Requires<[HasCLZERO]>; | TB, Requires<[HasCLZERO]>; | ||||
| let usesCustomInserter = 1 in { | let usesCustomInserter = 1 in { | ||||
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