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D145658: [Xtensa] Initial support of the ALU operations.
Differential Revision
D145662: [Xtensa] Implement asm representation of the Constant Pool.
Differential Revision
D145663: [Xtensa] Implement lowering constants.
Differential Revision
D145664: [Xtensa] Add support of the Xtensa function calls
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D145665: [Xtensa] Implement lowering ConstantPool and address operations.
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D145666: [Xtensa] Implement emitPrologue/emitEpilogue
Differential Revision
D145667: [Xtensa] Lower stack operations.
Differential Revision
D145668: [Xtensa] Implement lowering SELECT_CC, SETCC
Differential Revision
D146948: [Xtensa] Support for a variety of additional LLVM IR constructs.
Differential Revision
D146949: [Xtensa] Lower SHIFT PARTS and shift operations.
Differential Revision
D146950: [Xtensa] Implement load pseudo operations and patterns.
Differential Revision
D146951: [Xtensa] Support for variable arguments
Differential Revision
D146952: [Xtensa] Implement lowering BR_JT operation
Differential Revision
D146953: [Xtensa] Support for address intrinsics.
Differential Revision
D146955: [Xtensa] Implement volatile load/store.
Differential Revision
D146954: [Xtensa] Add basic support for inline asm constraints
Differential Revision
D146957: [Xtensa] Implement support for the BranchRelaxation
Differential Revision
D146956: [Xtensa] Implement branch analysis
Differential Revision
D145661: [Xtensa] Add Constant Pool
Differential Revision
D145660: [Xtensa] Codegen support for memory operations
Differential Revision
D64834: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions.
Differential Revision
·Closed
D64836: [Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions.
Differential Revision
·Closed
D64835: [Xtensa 9/10] Add basic support of Xtensa disassembler.
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·Closed
D64833: [Xtensa 7/10] Add Xtensa instruction printer.
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·Closed
D64832: [Xtensa 6/10] Add Xtensa basic assembler parser.
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·Closed
D64831: [Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality.
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·Closed
D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description.
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·Closed
D64829: [Xtensa 3/10] Add initial version of the Xtensa backend.
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·Closed
D64827: [Xtensa 2/10] Add Xtensa ELF definitions.
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·Closed
D64826: [Xtensa 1/10] Recognize Xtensa in triple parsing code.
Differential Revision
·Closed
D122479: [libcxx] Rename PS() macro to avoid clashing with Xtensa register name
Differential Revision
·Closed
W486 Xtensa commits
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rGff25800d4ba0: [Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core…
Diffusion Commit
rG71199af14c57: [Xtensa 9/10] Add basic support of Xtensa disassembler
Diffusion Commit
rG4e0c1d98d371: [Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor…
Diffusion Commit
rG2758a0139514: [Xtensa 7/10] Add Xtensa instruction printer
Diffusion Commit
rG52ecf023ed24: [Xtensa 6/10] Add Xtensa basic assembler parser
Diffusion Commit
rG6017209760c6: [Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality
Diffusion Commit
rG8a6552016c97: [Xtensa 4/10] Add basic *td files with Xtensa architecture description
Diffusion Commit
rG52804a7f22a2: [Xtensa 3/10] Add initial version of the Xtensa backend
Diffusion Commit
rG310f7652f796: [Xtensa 2/10] Add Xtensa ELF definitions
Diffusion Commit
rG8c618e8f53b1: [Xtensa 1/10] Recognize Xtensa in triple parsing code
Diffusion Commit
rG4fe6a5d69a61: [libc++] Rename PS() macro to avoid clashing with Xtensa register name
Diffusion Commit
rG28f6b2af48b4: [Xtensa] Add many code improvements of Xtensa backend in single patch (modify…
Diffusion Commit
rG0db191089d73: [Xtensa] Add FPR and BR register class
Diffusion Commit
rG04a9081ecc69: [Xtensa] Add Xtensa subtarget features.
Diffusion Commit
rG67730fbda7ff: [Xtensa] Implement lowering SELECT_CC, SETCC
Diffusion Commit
rG0de87badc447: [Xtensa] Implement emitPrologue/emitEpilogue
Diffusion Commit
rG0ceede6be37c: [Xtensa] Add support of the Xtensa function calls
Diffusion Commit
rGa89dc46e6058: [Xtensa] Implement assembler representation of the Constant Pool
Diffusion Commit
rG353906216f7a: [Xtensa] Add Constant Pool
Diffusion Commit
rG0bdd3c8d0556: [Xtensa] Initial codegen support for simple ALU operations
Diffusion Commit
rG6d74874a523e: [Xtensa] Add Xtensa target ABI support to clang
Diffusion Commit
rG7934cf9cee99: [Xtensa] Add Xtensa target to clang
Diffusion Commit
rG8d97fd948aa2: [Xtensa] Add support of the rest part of Xtensa Core Instructions. Add…
Diffusion Commit
rGad738ea51ac2: [Xtensa] Add basic support of Xtensa disassembler.
Diffusion Commit
rG497fe4e6527b: [Xtensa] Add descriptions of the Xtensa shift/load/store instructions.
Diffusion Commit
rGb468b816085b: [Xtensa] Add basic Xtensa instruction printer. Add basic tests of the Xtensa…
Diffusion Commit
rGadcda12c0df1: [Xtensa] Add Xtensa basic assembler parser.
Diffusion Commit
rGcdcba48e91a0: [Xtensa] Add Xtensa MCTargetDescr initial functionality.
Diffusion Commit
rGdc199157c6a8: [Xtensa] Add basic *td files with Xtensa architecture description, like Xtensa.
Diffusion Commit
rG4e8c960f035e: [Xtensa] Add initial version of the Xtensa backend.
Diffusion Commit
rGe581764ae0ff: [Xtensa] Add definitions and relocs for Xtensa ELF.
Diffusion Commit
rG0acf98628149: [Xtensa] Recognize Xtensa in triple parsing code
Diffusion Commit
D108961: [RISCV] MC relaxation for out-of-range conditional branch.
Differential Revision
·Closed
D140654: [MC] Use MCRegister instead of unsigned in MCInstPrinter (NFC)
Differential Revision
·Closed
D71569: [LoopFusion] Ensure that both loops are guarded or neither are guarded.
Differential Revision
D78438: [ELF] Fix "TLS attribute mismatch" false positives for STT_NOTYPE undefined symbols
Differential Revision
·Closed

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