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D69609.diff
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Sun, Apr 5, 2:02 PM

D69609.diff

Index: llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
===================================================================
--- llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
+++ llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
@@ -1,7 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=msp430-- < %s | FileCheck %s
-define i16 @testSimplifySetCC_0(i16 %a) {
+; Check the following conversion in TargetLowering::SimplifySetCC
+; (X & 8) != 0 --> (X & 8) >> 3
+define i16 @testSimplifySetCC_0(i16 %x) {
; CHECK-LABEL: testSimplifySetCC_0:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: bit #32, r12
@@ -9,13 +11,15 @@
; CHECK-NEXT: and #1, r12
; CHECK-NEXT: ret
entry:
- %and = and i16 %a, 32
+ %and = and i16 %x, 32
%cmp = icmp ne i16 %and, 0
%conv = zext i1 %cmp to i16
ret i16 %conv
}
-define i16 @testSimplifySetCC_1(i16 %a) {
+; Check the following conversion in TargetLowering::SimplifySetCC
+; (X & 8) == 8 --> (X & 8) >> 3
+define i16 @testSimplifySetCC_1(i16 %x) {
; CHECK-LABEL: testSimplifySetCC_1:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: bit #32, r12
@@ -23,38 +27,41 @@
; CHECK-NEXT: and #1, r12
; CHECK-NEXT: ret
entry:
- %and = and i16 %a, 32
+ %and = and i16 %x, 32
%cmp = icmp eq i16 %and, 32
%conv = zext i1 %cmp to i16
ret i16 %conv
}
-define i16 @testSiymplifySelect(i16 %a) {
-; CHECK-LABEL: testSiymplifySelect:
+; Check the following conversion in DAGCombiner::SimplifySelectCC
+; (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
+define i16 @testSiymplifySelectCC_0(i16 %x, i16 %a) {
+; CHECK-LABEL: testSiymplifySelectCC_0:
; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: mov r12, r13
+; CHECK-NEXT: mov r12, r14
; CHECK-NEXT: clr r12
-; CHECK-NEXT: bit #2048, r13
+; CHECK-NEXT: bit #2048, r14
; CHECK-NEXT: jeq .LBB2_2
; CHECK-NEXT: ; %bb.1: ; %entry
-; CHECK-NEXT: mov #3, r12
+; CHECK-NEXT: mov r13, r12
; CHECK-NEXT: .LBB2_2: ; %entry
; CHECK-NEXT: ret
entry:
- %and = and i16 %a, 2048
+ %and = and i16 %x, 2048
%cmp = icmp eq i16 %and, 0
- %cond = select i1 %cmp, i16 0, i16 3
+ %cond = select i1 %cmp, i16 0, i16 %a
ret i16 %cond
}
-define i16 @testExtendSignBit(i16 %a) {
-; CHECK-LABEL: testExtendSignBit:
+; Check the following conversion in DAGCombiner foldExtendedSignBitTest
+; sext i1 (setgt iN X, -1) --> sra (not X), (N - 1)
+define i16 @testExtendSignBit_0(i16 %x) {
+; CHECK-LABEL: testExtendSignBit_0:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: inv r12
; CHECK-NEXT: swpb r12
-; CHECK-NEXT: mov.b r12, r12
-; CHECK-NEXT: clrc
-; CHECK-NEXT: rrc r12
+; CHECK-NEXT: sxt r12
+; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
@@ -63,17 +70,21 @@
; CHECK-NEXT: rra r12
; CHECK-NEXT: ret
entry:
- %cmp = icmp sgt i16 %a, -1
- %cond = select i1 %cmp, i16 1, i16 0
+ %cmp = icmp sgt i16 %x, -1
+ %cond = sext i1 %cmp to i16
ret i16 %cond
}
-define i16 @testShiftAnd_0(i16 %a) {
-; CHECK-LABEL: testShiftAnd_0:
+; Check the following conversion in DAGCombiner foldExtendedSignBitTest
+; zext i1 (setgt iN X, -1) --> srl (not X), (N - 1)
+define i16 @testExtendSignBit_1(i16 %x) {
+; CHECK-LABEL: testExtendSignBit_1:
; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: inv r12
; CHECK-NEXT: swpb r12
-; CHECK-NEXT: sxt r12
-; CHECK-NEXT: rra r12
+; CHECK-NEXT: mov.b r12, r12
+; CHECK-NEXT: clrc
+; CHECK-NEXT: rrc r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
@@ -82,33 +93,37 @@
; CHECK-NEXT: rra r12
; CHECK-NEXT: ret
entry:
- %cmp = icmp slt i16 %a, 0
- %cond = select i1 %cmp, i16 -1, i16 0
+ %cmp = icmp sgt i16 %x, -1
+ %cond = zext i1 %cmp to i16
ret i16 %cond
}
-define i16 @testShiftAnd_1(i16 %a) {
-; CHECK-LABEL: testShiftAnd_1:
+; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd
+; select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
+define i16 @testShiftAnd_0(i16 %x, i16 %a) {
+; CHECK-LABEL: testShiftAnd_0:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: swpb r12
-; CHECK-NEXT: mov.b r12, r12
-; CHECK-NEXT: clrc
-; CHECK-NEXT: rrc r12
+; CHECK-NEXT: sxt r12
+; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
; CHECK-NEXT: rra r12
+; CHECK-NEXT: and r13, r12
; CHECK-NEXT: ret
entry:
- %cmp = icmp slt i16 %a, 0
- %cond = select i1 %cmp, i16 1, i16 0
+ %cmp = icmp slt i16 %x, 0
+ %cond = select i1 %cmp, i16 %a, i16 0
ret i16 %cond
}
-define i16 @testShiftAnd_2(i16 %a) {
-; CHECK-LABEL: testShiftAnd_2:
+; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd
+; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit
+define i16 @testShiftAnd_1(i16 %x) {
+; CHECK-LABEL: testShiftAnd_1:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: swpb r12
; CHECK-NEXT: mov.b r12, r12
@@ -122,41 +137,23 @@
; CHECK-NEXT: and #2, r12
; CHECK-NEXT: ret
entry:
- %cmp = icmp slt i16 %a, 0
+ %cmp = icmp slt i16 %x, 0
%cond = select i1 %cmp, i16 2, i16 0
ret i16 %cond
}
-define i16 @testShiftAnd_3(i16 %a) {
-; CHECK-LABEL: testShiftAnd_3:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: swpb r12
-; CHECK-NEXT: sxt r12
-; CHECK-NEXT: rra r12
-; CHECK-NEXT: rra r12
-; CHECK-NEXT: rra r12
-; CHECK-NEXT: rra r12
-; CHECK-NEXT: rra r12
-; CHECK-NEXT: rra r12
-; CHECK-NEXT: rra r12
-; CHECK-NEXT: and #3, r12
-; CHECK-NEXT: ret
-entry:
- %cmp = icmp slt i16 %a, 0
- %cond = select i1 %cmp, i16 3, i16 0
- ret i16 %cond
-}
-
-define i16 @testShiftAnd_4(i16 %a, i16 %b) {
-; CHECK-LABEL: testShiftAnd_4:
+; Check the following conversion in DAGCombiner::SimplifySelectCC
+; select C, 16, 0 -> shl C, 4
+define i16 @testSiymplifySelectCC_1(i16 %a, i16 %b) {
+; CHECK-LABEL: testSiymplifySelectCC_1:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov r12, r14
; CHECK-NEXT: mov #1, r12
; CHECK-NEXT: cmp r14, r13
-; CHECK-NEXT: jl .LBB8_2
+; CHECK-NEXT: jl .LBB7_2
; CHECK-NEXT: ; %bb.1: ; %entry
; CHECK-NEXT: clr r12
-; CHECK-NEXT: .LBB8_2: ; %entry
+; CHECK-NEXT: .LBB7_2: ; %entry
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12
; CHECK-NEXT: add r12, r12

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