diff --git a/llvm/test/CodeGen/AArch64/speculation-hardening.ll b/llvm/test/CodeGen/AArch64/speculation-hardening.ll
--- a/llvm/test/CodeGen/AArch64/speculation-hardening.ll
+++ b/llvm/test/CodeGen/AArch64/speculation-hardening.ll
@@ -16,9 +16,9 @@
 ; SLH:  mov [[TMPREG:x[0-9]+]], sp
 ; SLH:  and [[TMPREG]], [[TMPREG]], x16
 ; SLH:  mov sp, [[TMPREG]]
-; NOSLH-NOT:  mov [[TMPREG:x[0-9]+]], sp
-; NOSLH-NOT:  and [[TMPREG]], [[TMPREG]], x16
-; NOSLH-NOT:  mov sp, [[TMPREG]]
+; NOSLH-NOT:  mov {{x[0-9]+}}, sp
+; NOSLH-NOT:  and [[TMPREG:x[0-9]+]], [[TMPREG]], x16
+; NOSLH-NOT:  mov sp, {{x[0-9]+}}
   %call = tail call i32 @tail_callee(i32 %i)
 ; SLH:  cmp sp, #0
 ; SLH:  csetm x16, ne
@@ -45,9 +45,9 @@
 ; SLH:  mov [[TMPREG:x[0-9]+]], sp
 ; SLH:  and [[TMPREG]], [[TMPREG]], x16
 ; SLH:  mov sp, [[TMPREG]]
-; NOSLH-NOT:  mov [[TMPREG:x[0-9]+]], sp
-; NOSLH-NOT:  and [[TMPREG]], [[TMPREG]], x16
-; NOSLH-NOT:  mov sp, [[TMPREG]]
+; NOSLH-NOT:  mov {{x[0-9]+}}, sp
+; NOSLH-NOT:  and [[TMPREG:x[0-9]+]], [[TMPREG]], x16
+; NOSLH-NOT:  mov sp, {{x[0-9]+}}
   ret i32 %retval.0
 }
 
@@ -57,9 +57,9 @@
 ; SLH:     mov [[TMPREG:x[0-9]+]], sp
 ; SLH:     and [[TMPREG]], [[TMPREG]], x16
 ; SLH:     mov sp, [[TMPREG]]
-; NOSLH-NOT:     mov [[TMPREG:x[0-9]+]], sp
-; NOSLH-NOT:     and [[TMPREG]], [[TMPREG]], x16
-; NOSLH-NOT:     mov sp, [[TMPREG]]
+; NOSLH-NOT:     mov {{x[0-9]+}}, sp
+; NOSLH-NOT:     and [[TMPREG:x[0-9]+]], [[TMPREG]], x16
+; NOSLH-NOT:     mov sp, {{x[0-9]+}}
 ; SLH:     b tail_callee
 ; SLH-NOT:        cmp sp, #0
   %call = tail call i32 @tail_callee(i32 %a)