Index: lib/Target/R600/AMDGPUISelDAGToDAG.cpp
===================================================================
--- lib/Target/R600/AMDGPUISelDAGToDAG.cpp
+++ lib/Target/R600/AMDGPUISelDAGToDAG.cpp
@@ -696,16 +696,13 @@
   }
 
   const Value *MemVal = N->getMemOperand()->getValue();
-  if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
-      !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
-      !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
-      !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
-      !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
-      !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
-      !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
-    return true;
-  }
-  return false;
+  return !checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
+         !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
+         !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
+         !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
+         !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
+         !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
+         !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS);
 }
 
 const char *AMDGPUDAGToDAGISel::getPassName() const {
Index: lib/Target/R600/AMDGPUISelLowering.cpp
===================================================================
--- lib/Target/R600/AMDGPUISelLowering.cpp
+++ lib/Target/R600/AMDGPUISelLowering.cpp
@@ -757,10 +757,7 @@
   if (!GVar || !GVar->hasInitializer())
     return false;
 
-  if (isa<UndefValue>(GVar->getInitializer()))
-    return false;
-
-  return true;
+  return !isa<UndefValue>(GVar->getInitializer());
 }
 
 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
Index: lib/Target/R600/R600InstrInfo.cpp
===================================================================
--- lib/Target/R600/R600InstrInfo.cpp
+++ lib/Target/R600/R600InstrInfo.cpp
@@ -913,9 +913,7 @@
     if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
       return false;
     // TODO: We don't support KC merging atm
-    if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
-      return false;
-    return true;
+    return MI->getOperand(3).getImm() == 0 && MI->getOperand(4).getImm() == 0;
   } else if (isVector(*MI)) {
     return false;
   } else {
Index: lib/Target/R600/R600Packetizer.cpp
===================================================================
--- lib/Target/R600/R600Packetizer.cpp
+++ lib/Target/R600/R600Packetizer.cpp
@@ -178,9 +178,7 @@
       return true;
     // XXX: This can be removed once the packetizer properly handles all the
     // LDS instruction group restrictions.
-    if (TII->isLDSInstr(MI->getOpcode()))
-      return true;
-    return false;
+    return TII->isLDSInstr(MI->getOpcode());
   }
 
   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
@@ -214,10 +212,7 @@
                  TII->definesAddressRegister(MIJ);
     bool ARUse = TII->usesAddressRegister(MII) ||
                  TII->usesAddressRegister(MIJ);
-    if (ARDef && ARUse)
-      return false;
-
-    return true;
+    return !ARDef || !ARUse;
   }
 
   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
Index: lib/Target/R600/SIInsertWaits.cpp
===================================================================
--- lib/Target/R600/SIInsertWaits.cpp
+++ lib/Target/R600/SIInsertWaits.cpp
@@ -206,10 +206,7 @@
       return true;
 
     MachineOperand *Data1 = TII->getNamedOperand(MI, AMDGPU::OpName::data1);
-    if (Data1 && Op.isIdenticalTo(*Data1))
-      return true;
-
-    return false;
+    return Data1 && Op.isIdenticalTo(*Data1);
   }
 
   // NOTE: This assumes that the value operand is before the
Index: lib/Target/R600/SIInstrInfo.cpp
===================================================================
--- lib/Target/R600/SIInstrInfo.cpp
+++ lib/Target/R600/SIInstrInfo.cpp
@@ -303,10 +303,7 @@
   if (isSMRD(Opc0) && isSMRD(Opc1))
     return true;
 
-  if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
-    return true;
-
-  return false;
+  return (isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1));
 }
 
 void
@@ -1260,14 +1257,9 @@
     return true;
 
   // SGPRs use the constant bus
-  if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
-      (!MO.isImplicit() &&
-      (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
-       AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
-    return true;
-  }
-
-  return false;
+  return MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
+         (!MO.isImplicit() && (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
+                               AMDGPU::SGPR_64RegClass.contains(MO.getReg())));
 }
 
 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
Index: lib/Target/R600/SIShrinkInstructions.cpp
===================================================================
--- lib/Target/R600/SIShrinkInstructions.cpp
+++ lib/Target/R600/SIShrinkInstructions.cpp
@@ -113,10 +113,7 @@
   if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
     return false;
 
-  if (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp))
-    return false;
-
-  return true;
+  return !TII->hasModifiersSet(MI, AMDGPU::OpName::clamp);
 }
 
 /// \brief This function checks \p MI for operands defined by a move immediate