Index: lib/Target/PowerPC/PPCFastISel.cpp
===================================================================
--- lib/Target/PowerPC/PPCFastISel.cpp
+++ lib/Target/PowerPC/PPCFastISel.cpp
@@ -277,11 +277,7 @@
 
   // If this is a type than can be sign or zero-extended to a basic operation
   // go ahead and accept it now.
-  if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
-    return true;
-  }
-
-  return false;
+  return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32;
 }
 
 bool PPCFastISel::isValueAvailable(const Value *V) const {
@@ -289,10 +285,7 @@
     return true;
 
   const auto *I = cast<Instruction>(V);
-  if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
-    return true;
-
-  return false;
+  return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
 }
 
 // Given a value Obj, create an Address object Addr that represents its
@@ -728,10 +721,7 @@
   if (!PPCComputeAddress(I->getOperand(1), Addr))
     return false;
 
-  if (!PPCEmitStore(VT, SrcReg, Addr))
-    return false;
-
-  return true;
+  return PPCEmitStore(VT, SrcReg, Addr);
 }
 
 // Attempt to fast-select a branch instruction.
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1561,10 +1561,7 @@
           return false;
         }
 
-        if (VRI.RLAmt != EffRLAmt)
-          return false;
-
-        return true;
+        return VRI.RLAmt == EffRLAmt;
       };
 
       for (auto &BG : BitGroups) {
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11201,9 +11201,7 @@
   assert(Ty->isIntegerTy());
 
   unsigned BitSize = Ty->getPrimitiveSizeInBits();
-  if (BitSize == 0 || BitSize > 64)
-    return false;
-  return true;
+  return BitSize != 0 && BitSize <= 64;
 }
 
 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
Index: lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.cpp
+++ lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1331,11 +1331,7 @@
   if (P1 == PPC::PRED_LE &&
       (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
     return true;
-  if (P1 == PPC::PRED_GE &&
-      (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
-    return true;
-
-  return false;
+  return P1 == PPC::PRED_GE && (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ);
 }
 
 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
Index: lib/Target/PowerPC/PPCRegisterInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -901,10 +901,7 @@
 }
 
 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
-  if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
-    return false;
-
-  return true;
+  return !MF.getFunction()->hasFnAttribute("no-realign-stack");
 }
 
 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
Index: lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
===================================================================
--- lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+++ lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
@@ -157,9 +157,7 @@
   bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) {
     if (TargetRegisterInfo::isVirtualRegister(Reg))
       return RC->hasSubClassEq(MRI->getRegClass(Reg));
-    if (RC->contains(Reg))
-      return true;
-    return false;
+    return RC->contains(Reg);
   }
 
   // Return true iff the given register is a full vector register.