Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -931,17 +931,14 @@
     unsigned R0 = RegList.List->front();
     unsigned R1 = RegList.List->back();
 
-    if ((R0 == Mips::A1 && R1 == Mips::A2) ||
-        (R0 == Mips::A1 && R1 == Mips::A3) ||
-        (R0 == Mips::A2 && R1 == Mips::A3) ||
-        (R0 == Mips::A0 && R1 == Mips::S5) ||
-        (R0 == Mips::A0 && R1 == Mips::S6) ||
-        (R0 == Mips::A0 && R1 == Mips::A1) ||
-        (R0 == Mips::A0 && R1 == Mips::A2) ||
-        (R0 == Mips::A0 && R1 == Mips::A3))
-      return true;
-
-    return false;
+    return (R0 == Mips::A1 && R1 == Mips::A2) ||
+           (R0 == Mips::A1 && R1 == Mips::A3) ||
+           (R0 == Mips::A2 && R1 == Mips::A3) ||
+           (R0 == Mips::A0 && R1 == Mips::S5) ||
+           (R0 == Mips::A0 && R1 == Mips::S6) ||
+           (R0 == Mips::A0 && R1 == Mips::A1) ||
+           (R0 == Mips::A0 && R1 == Mips::A2) ||
+           (R0 == Mips::A0 && R1 == Mips::A3);
   }
 
   StringRef getToken() const {
@@ -1879,11 +1876,8 @@
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
-  if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
-                    Is32BitImm, IDLoc, Instructions))
-    return true;
-
-  return false;
+  return loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
+                       Is32BitImm, IDLoc, Instructions);
 }
 
 bool
@@ -1902,11 +1896,8 @@
   const MCOperand &SrcRegOp = Inst.getOperand(1);
   assert(SrcRegOp.isReg() && "expected register operand kind");
 
-  if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
-                    Is32BitImm, IDLoc, Instructions))
-    return true;
-
-  return false;
+  return loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), SrcRegOp.getReg(),
+                       Is32BitImm, IDLoc, Instructions);
 }
 
 bool
@@ -1923,11 +1914,8 @@
     return false;
   }
 
-  if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
-                    Is32BitImm, IDLoc, Instructions))
-    return true;
-
-  return false;
+  return loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
+                       Is32BitImm, IDLoc, Instructions);
 }
 
 void MipsAsmParser::expandLoadAddressSym(
Index: lib/Target/Mips/MipsFastISel.cpp
===================================================================
--- lib/Target/Mips/MipsFastISel.cpp
+++ lib/Target/Mips/MipsFastISel.cpp
@@ -496,10 +496,7 @@
 
   // If this is a type than can be sign or zero-extended to a basic operation
   // go ahead and accept it now.
-  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
-    return true;
-
-  return false;
+  return VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16;
 }
 
 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
@@ -508,9 +505,7 @@
   // We will extend this in a later patch:
   //   If this is a type than can be sign or zero-extended to a basic operation
   //   go ahead and accept it now.
-  if (VT == MVT::i8 || VT == MVT::i16)
-    return true;
-  return false;
+  return VT == MVT::i8 || VT == MVT::i16;
 }
 // Because of how EmitCmp is called with fast-isel, you can
 // end up with redundant "andi" instructions after the sequences emitted below.
@@ -824,9 +819,7 @@
   if (!computeAddress(I->getOperand(1), Addr))
     return false;
 
-  if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
-    return false;
-  return true;
+  return emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment());
 }
 
 //
Index: lib/Target/Mips/MipsSEISelDAGToDAG.cpp
===================================================================
--- lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -389,10 +389,7 @@
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
-  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
-    return true;
-
-  return false;
+  return selectAddrFrameIndexOffset(Addr, Base, Offset, 9);
 }
 
 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
@@ -400,10 +397,7 @@
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
-  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
-    return true;
-
-  return false;
+  return selectAddrFrameIndexOffset(Addr, Base, Offset, 10);
 }
 
 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
@@ -412,10 +406,7 @@
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
-  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
-    return true;
-
-  return false;
+  return selectAddrFrameIndexOffset(Addr, Base, Offset, 12);
 }
 
 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
@@ -423,10 +414,7 @@
   if (selectAddrFrameIndex(Addr, Base, Offset))
     return true;
 
-  if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
-    return true;
-
-  return false;
+  return selectAddrFrameIndexOffset(Addr, Base, Offset, 16);
 }
 
 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
@@ -462,10 +450,7 @@
   if (selectAddrRegImm10(Addr, Base, Offset))
     return true;
 
-  if (selectAddrDefault(Addr, Base, Offset))
-    return true;
-
-  return false;
+  return selectAddrDefault(Addr, Base, Offset);
 }
 
 // Select constant vector splats.
Index: lib/Target/Mips/MipsSEISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsSEISelLowering.cpp
+++ lib/Target/Mips/MipsSEISelLowering.cpp
@@ -2300,9 +2300,7 @@
     return true;
   if (isa<ConstantSDNode>(Op))
     return true;
-  if (isa<ConstantFPSDNode>(Op))
-    return true;
-  return false;
+  return isa<ConstantFPSDNode>(Op);
 }
 
 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {