Index: lib/Target/Hexagon/HexagonCopyToCombine.cpp
===================================================================
--- lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -177,11 +177,8 @@
          "Assume individual instructions are of a combinable type");
 
   // There is no combine of two constant extended values.
-  if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
-      isGreaterThanNBitTFRI<6>(LowRegInst))
-    return false;
-
-  return true;
+  return !(isGreaterThanNBitTFRI<8>(HighRegInst) &&
+           isGreaterThanNBitTFRI<6>(LowRegInst));
 }
 
 static bool isEvenReg(unsigned Reg) {
Index: lib/Target/Hexagon/HexagonExpandCondsets.cpp
===================================================================
--- lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -223,9 +223,7 @@
   if (F == Map.end())
     return false;
   unsigned Mask = getMaskForSub(RR.Sub) | Exec;
-  if (Mask & F->second)
-    return true;
-  return false;
+  return Mask & F->second;
 }
 
 
Index: lib/Target/Hexagon/HexagonFrameLowering.cpp
===================================================================
--- lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1203,9 +1203,7 @@
   if (!MFI->hasVarSizedObjects())
     return false;
   unsigned MaxA = MFI->getMaxAlignment();
-  if (MaxA <= getStackAlignment())
-    return false;
-  return true;
+  return MaxA > getStackAlignment();
 }
 
 
Index: lib/Target/Hexagon/HexagonHardwareLoops.cpp
===================================================================
--- lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1449,10 +1449,7 @@
   // OK - this is a hack that needs to be improved. We really need to analyze
   // the instructions performed on the initial value. This works on the simplest
   // cases only.
-  if (!Def->isCopy() && !Def->isPHI())
-    return false;
-
-  return true;
+  return Def->isCopy() || Def->isPHI();
 }
 
 bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
Index: lib/Target/Hexagon/HexagonISelLowering.cpp
===================================================================
--- lib/Target/Hexagon/HexagonISelLowering.cpp
+++ lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -397,10 +397,7 @@
 
 bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
   // If either no tail call or told not to tail call at all, don't.
-  if (!CI->isTailCall() || HTM.Options.DisableTailCalls)
-    return false;
-
-  return true;
+  return CI->isTailCall() && !HTM.Options.DisableTailCalls;
 }
 
 /// LowerCallResult - Lower the result values of an ISD::CALL into the
@@ -987,9 +984,7 @@
       N.getOperand(0).getOpcode() == ISD::AssertSext)
     return true;
   // We have sign-extended loads.
-  if (N.getOpcode() == ISD::LOAD)
-    return true;
-  return false;
+  return N.getOpcode() == ISD::LOAD;
 }
 
 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
Index: lib/Target/Hexagon/HexagonInstrInfo.cpp
===================================================================
--- lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -849,10 +849,7 @@
   if (isNewValueJump(MI))
     return true;
 
-  if (isNewValueStore(MI))
-    return true;
-
-  return false;
+  return isNewValueStore(MI);
 }
 
 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
@@ -1618,9 +1615,7 @@
 
 
 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
-  if (isNewValue(MI) && isBranch(MI))
-    return true;
-  return false;
+  return isNewValue(MI) && isBranch(MI);
 }
 
 bool HexagonInstrInfo::isNewValueJump(Opcode_t Opcode) const {
@@ -1775,10 +1770,7 @@
     return false;
 
   // Terminators and labels can't be scheduled around.
-  if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
-    return true;
-
-  return false;
+  return MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm();
 }
 
 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
@@ -1944,9 +1936,7 @@
     default:
       return false;
     }
-    if (NonExtOpcode < 0)
-      return false;
-    return true;
+    return NonExtOpcode >= 0;
   }
   return false;
 }
Index: lib/Target/Hexagon/HexagonMachineScheduler.cpp
===================================================================
--- lib/Target/Hexagon/HexagonMachineScheduler.cpp
+++ lib/Target/Hexagon/HexagonMachineScheduler.cpp
@@ -275,10 +275,7 @@
     return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
 
   unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
-  if (IssueCount + uops > SchedModel->getIssueWidth())
-    return true;
-
-  return false;
+  return IssueCount + uops > SchedModel->getIssueWidth();
 }
 
 void ConvergingVLIWScheduler::VLIWSchedBoundary::releaseNode(SUnit *SU,
Index: lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
===================================================================
--- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -411,14 +411,9 @@
   const MCInstrDesc& TID = MI->getDesc();
                                     // bug 5670: until that is fixed,
                                     // this portion is disabled.
-  if (   TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
-      || QII->isConditionalTransfer(MI)
-      || QII->isConditionalALU32(MI)
-      || QII->isConditionalLoad(MI)
-      || QII->isConditionalStore(MI)) {
-    return true;
-  }
-  return false;
+  return TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
+         || QII->isConditionalTransfer(MI) || QII->isConditionalALU32(MI) ||
+         QII->isConditionalLoad(MI) || QII->isConditionalStore(MI);
 }
 
 
@@ -979,10 +974,7 @@
   // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
   // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
   // They must not be grouped with other instructions in a packet.
-  if (IsSchedBarrier(MI))
-    return true;
-
-  return false;
+  return IsSchedBarrier(MI);
 }
 
 // isLegalToPacketizeTogether: