Index: lib/Target/Hexagon/HexagonCopyToCombine.cpp
===================================================================
--- lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -178,11 +178,8 @@
          "Assume individual instructions are of a combinable type");
 
   // There is no combine of two constant extended values.
-  if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
-      isGreaterThanNBitTFRI<6>(LowRegInst))
-    return false;
-
-  return true;
+  return !(isGreaterThanNBitTFRI<8>(HighRegInst) &&
+           isGreaterThanNBitTFRI<6>(LowRegInst));
 }
 
 static bool isEvenReg(unsigned Reg) {
Index: lib/Target/Hexagon/HexagonEarlyIfConv.cpp
===================================================================
--- lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -543,10 +543,7 @@
     return false;
 
   DEBUG(dbgs() << "Total number of predicate registers: " << PredDefs << "\n");
-  if (PredDefs > 4)
-    return false;
-
-  return true;
+  return PredDefs <= 4;
 }
 
 
Index: lib/Target/Hexagon/HexagonExpandCondsets.cpp
===================================================================
--- lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -232,9 +232,7 @@
   if (F == Map.end())
     return false;
   unsigned Mask = getMaskForSub(RR.Sub) | Exec;
-  if (Mask & F->second)
-    return true;
-  return false;
+  return static_cast<bool>(Mask & F->second);
 }
 
 
Index: lib/Target/Hexagon/HexagonFrameLowering.cpp
===================================================================
--- lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1391,9 +1391,7 @@
   if (!MFI->hasVarSizedObjects())
     return false;
   unsigned MaxA = MFI->getMaxAlignment();
-  if (MaxA <= getStackAlignment())
-    return false;
-  return true;
+  return MaxA > getStackAlignment();
 }
 
 
Index: lib/Target/Hexagon/HexagonHardwareLoops.cpp
===================================================================
--- lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1448,10 +1448,7 @@
   // OK - this is a hack that needs to be improved. We really need to analyze
   // the instructions performed on the initial value. This works on the simplest
   // cases only.
-  if (!Def->isCopy() && !Def->isPHI())
-    return false;
-
-  return true;
+  return !(!Def->isCopy() && !Def->isPHI());
 }
 
 bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
Index: lib/Target/Hexagon/HexagonISelLowering.cpp
===================================================================
--- lib/Target/Hexagon/HexagonISelLowering.cpp
+++ lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -399,10 +399,7 @@
   // If either no tail call or told not to tail call at all, don't.
   auto Attr =
       CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
-  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
-    return false;
-
-  return true;
+  return !(!CI->isTailCall() || Attr.getValueAsString() == "true");
 }
 
 /// LowerCallResult - Lower the result values of an ISD::CALL into the
Index: lib/Target/Hexagon/HexagonInstrInfo.cpp
===================================================================
--- lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1671,9 +1671,7 @@
 
 
 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
-  if (isNewValue(MI) && isBranch(MI))
-    return true;
-  return false;
+  return isNewValue(MI) && isBranch(MI);
 }
 
 bool HexagonInstrInfo::isNewValueJump(Opcode_t Opcode) const {
@@ -1828,10 +1826,7 @@
     return false;
 
   // Terminators and labels can't be scheduled around.
-  if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
-    return true;
-
-  return false;
+  return MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm();
 }
 
 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
@@ -1997,9 +1992,7 @@
     default:
       return false;
     }
-    if (NonExtOpcode < 0)
-      return false;
-    return true;
+    return NonExtOpcode >= 0;
   }
   return false;
 }
Index: lib/Target/Hexagon/HexagonMachineScheduler.cpp
===================================================================
--- lib/Target/Hexagon/HexagonMachineScheduler.cpp
+++ lib/Target/Hexagon/HexagonMachineScheduler.cpp
@@ -279,10 +279,7 @@
     return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
 
   unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
-  if (IssueCount + uops > SchedModel->getIssueWidth())
-    return true;
-
-  return false;
+  return IssueCount + uops > SchedModel->getIssueWidth();
 }
 
 void ConvergingVLIWScheduler::VLIWSchedBoundary::releaseNode(SUnit *SU,
Index: lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
===================================================================
--- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -409,14 +409,11 @@
   const MCInstrDesc& TID = MI->getDesc();
                                     // bug 5670: until that is fixed,
                                     // this portion is disabled.
-  if (   TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
+  return TID.isConditionalBranch()  // && !IsRegisterJump(MI)) ||
       || QII->isConditionalTransfer(MI)
       || QII->isConditionalALU32(MI)
       || QII->isConditionalLoad(MI)
-      || QII->isConditionalStore(MI)) {
-    return true;
-  }
-  return false;
+      || QII->isConditionalStore(MI);
 }