Index: clang/lib/Headers/uintrintrin.h
===================================================================
--- clang/lib/Headers/uintrintrin.h
+++ clang/lib/Headers/uintrintrin.h
@@ -20,6 +20,13 @@
 
 #ifdef __x86_64__
 
+struct __uintr_frame
+{
+  unsigned long long rip;
+  unsigned long long rflags;
+  unsigned long long rsp;
+};
+
 /// Clears the user interrupt flag (UIF). Its effect takes place immediately: a
 ///    user interrupt cannot be delivered on the instruction boundary following
 ///    CLUI. Can be executed only if CR4.UINT = 1, the logical processor is in
Index: llvm/lib/Target/X86/X86ExpandPseudo.cpp
===================================================================
--- llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -316,7 +316,9 @@
     X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, true);
     // Replace pseudo with machine iret
     BuildMI(MBB, MBBI, DL,
-            TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32));
+            TII->get(STI->is64Bit()
+                         ? (STI->hasUINTR() ? X86::UIRET : X86::IRET64)
+                         : X86::IRET32));
     MBB.erase(MBBI);
     return true;
   }
Index: llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/x86-64-intrcc-uintr.ll
@@ -0,0 +1,111 @@
+; RUN: llc < %s | FileCheck %s
+; RUN: llc -O0 < %s | FileCheck %s -check-prefix=CHECK0
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.__uintr_frame = type { i64, i64, i64 }
+
+; #include <x86gprintrin.h>
+;
+; void
+; __attribute__ ((interrupt))
+; test_uintr_isr_cc_empty(struct __uintr_frame *frame, unsigned long long uirrv)
+; {
+; }
+
+define dso_local x86_intrcc void @test_uintr_isr_cc_empty(%struct.__uintr_frame* nocapture byval(%struct.__uintr_frame) %frame, i64 %uirrv) #0 {
+; CHECK-LABEL: test_uintr_isr_cc_empty:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    cld
+; CHECK-NEXT:    addq $16, %rsp
+; CHECK-NEXT:    uiret
+;
+; CHECK0-LABEL: test_uintr_isr_cc_empty:
+; CHECK0:       # %bb.0: # %entry
+; CHECK0-NEXT:    pushq %rax
+; CHECK0-NEXT:    cld
+; CHECK0-NEXT:    addq $16, %rsp
+; CHECK0-NEXT:    uiret
+entry:
+  ret void
+}
+
+; unsigned long long g_rip;
+; unsigned long long g_rflags;
+; unsigned long long g_rsp;
+; unsigned long long g_uirrv;
+;
+; void
+; __attribute__((interrupt))
+; test_uintr_isr_cc_args(struct __uintr_frame *frame, unsigned long long uirrv)
+; {
+;   g_rip = frame->rip;
+;   g_rflags = frame->rflags;
+;   g_rsp = frame->rsp;
+;   g_uirrv = uirrv;
+; }
+@g_rip = dso_local local_unnamed_addr global i64 0, align 8
+@g_rflags = dso_local local_unnamed_addr global i64 0, align 8
+@g_rsp = dso_local local_unnamed_addr global i64 0, align 8
+@g_uirrv = dso_local local_unnamed_addr global i64 0, align 8
+
+define dso_local x86_intrcc void @test_uintr_isr_cc_args(%struct.__uintr_frame* nocapture readonly byval(%struct.__uintr_frame) %frame, i64 %uirrv) #0 {
+; CHECK-LABEL: test_uintr_isr_cc_args:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    pushq %rdx
+; CHECK-NEXT:    pushq %rcx
+; CHECK-NEXT:    cld
+; CHECK-NEXT:    movq 32(%rsp), %rax
+; CHECK-NEXT:    movq 40(%rsp), %rcx
+; CHECK-NEXT:    movq 48(%rsp), %rdx
+; CHECK-NEXT:    movq %rcx, g_rip(%rip)
+; CHECK-NEXT:    movq %rdx, g_rflags(%rip)
+; CHECK-NEXT:    movq 56(%rsp), %rcx
+; CHECK-NEXT:    movq %rcx, g_rsp(%rip)
+; CHECK-NEXT:    movq %rax, g_uirrv(%rip)
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    popq %rdx
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    addq $16, %rsp
+; CHECK-NEXT:    uiret
+;
+; CHECK0-LABEL: test_uintr_isr_cc_args:
+; CHECK0:       # %bb.0: # %entry
+; CHECK0-NEXT:    pushq %rax
+; CHECK0-NEXT:    pushq %rax
+; CHECK0-NEXT:    pushq %rdx
+; CHECK0-NEXT:    pushq %rcx
+; CHECK0-NEXT:    cld
+; CHECK0-NEXT:    movq 32(%rsp), %rax
+; CHECK0-NEXT:    leaq 40(%rsp), %rcx
+; CHECK0-NEXT:    movq (%rcx), %rdx
+; CHECK0-NEXT:    movq %rdx, g_rip(%rip)
+; CHECK0-NEXT:    movq 8(%rcx), %rdx
+; CHECK0-NEXT:    movq %rdx, g_rflags(%rip)
+; CHECK0-NEXT:    movq 16(%rcx), %rcx
+; CHECK0-NEXT:    movq %rcx, g_rsp(%rip)
+; CHECK0-NEXT:    movq %rax, g_uirrv(%rip)
+; CHECK0-NEXT:    popq %rcx
+; CHECK0-NEXT:    popq %rdx
+; CHECK0-NEXT:    popq %rax
+; CHECK0-NEXT:    addq $16, %rsp
+; CHECK0-NEXT:    uiret
+entry:
+  %rip = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 0
+  %0 = load i64, i64* %rip, align 8
+  store i64 %0, i64* @g_rip, align 8
+  %rflags = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 1
+  %1 = load i64, i64* %rflags, align 8
+  store i64 %1, i64* @g_rflags, align 8
+  %rsp = getelementptr inbounds %struct.__uintr_frame, %struct.__uintr_frame* %frame, i64 0, i32 2
+  %2 = load i64, i64* %rsp, align 8
+  store i64 %2, i64* @g_rsp, align 8
+  store i64 %uirrv, i64* @g_uirrv, align 8
+  ret void
+}
+
+attributes #0 = { nofree norecurse nounwind willreturn "disable-tail-calls"="true" "frame-pointer"="none" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+uintr" "tune-cpu"="generic" }