diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -629,6 +629,8 @@
     uint64_t AlignOffset) const {
   assert(Offset && "null offset");
 
+  const bool NeedsDwarfCFI = needsDwarfCFI(MF);
+  const bool HasFP = hasFP(MF);
   const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
   const X86TargetLowering &TLI = *STI.getTargetLowering();
   const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
@@ -672,11 +674,23 @@
 
   // save loop bound
   {
+    const unsigned BoundOffset = Offset / StackProbeSize * StackProbeSize;
     const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, Offset);
     BuildMI(MBB, MBBI, DL, TII.get(SUBOpc), FinalStackProbed)
         .addReg(FinalStackProbed)
-        .addImm(Offset / StackProbeSize * StackProbeSize)
+        .addImm(BoundOffset)
         .setMIFlag(MachineInstr::FrameSetup);
+
+    // TODO: generate DWARF information for 32bit architecture
+    // didn't generate dwarf information on 32bit, because R11D is not usable
+    // and decide a safe register could be complicate or with extra cost
+    if (!HasFP && NeedsDwarfCFI && Uses64BitFramePtr) {
+      BuildCFI(MBB, MBBI, DL,
+               MCCFIInstruction::createDefCfaRegister(
+                   nullptr, TRI->getDwarfRegNum(FinalStackProbed, true)));
+      BuildCFI(MBB, MBBI, DL,
+               MCCFIInstruction::createAdjustCfaOffset(nullptr, BoundOffset));
+    }
   }
 
   // allocate a page
@@ -716,14 +730,23 @@
 
   // handle tail
   unsigned TailOffset = Offset % StackProbeSize;
+  MachineBasicBlock::iterator TailMBBIter = tailMBB->begin();
   if (TailOffset) {
     const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, TailOffset);
-    BuildMI(*tailMBB, tailMBB->begin(), DL, TII.get(Opc), StackPtr)
+    BuildMI(*tailMBB, TailMBBIter, DL, TII.get(Opc), StackPtr)
         .addReg(StackPtr)
         .addImm(TailOffset)
         .setMIFlag(MachineInstr::FrameSetup);
   }
 
+  // TODO: generate DWARF information for 32bit architecture
+  // didn't generate dwarf information on 32bit, because R11D is not usable
+  // and decide a safe register could be complicate or with extra cost
+  if (!HasFP && NeedsDwarfCFI && Uses64BitFramePtr) {
+    BuildCFI(*tailMBB, TailMBBIter, DL,
+             MCCFIInstruction::createDefCfaRegister(
+                 nullptr, TRI->getDwarfRegNum(StackPtr, true)));
+  }
   // Update Live In information
   recomputeLiveIns(*testMBB);
   recomputeLiveIns(*tailMBB);
diff --git a/llvm/test/CodeGen/X86/stack-clash-large.ll b/llvm/test/CodeGen/X86/stack-clash-large.ll
--- a/llvm/test/CodeGen/X86/stack-clash-large.ll
+++ b/llvm/test/CodeGen/X86/stack-clash-large.ll
@@ -7,6 +7,8 @@
 ; CHECK-X86-64:       # %bb.0:
 ; CHECK-X86-64-NEXT:    movq %rsp, %r11
 ; CHECK-X86-64-NEXT:    subq $69632, %r11 # imm = 0x11000
+; CHECK-X86-64-NEXT:    .cfi_def_cfa_register %r11
+; CHECK-X86-64-NEXT:    .cfi_adjust_cfa_offset 69632
 ; CHECK-X86-64-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
 ; CHECK-X86-64-NEXT:    subq $4096, %rsp # imm = 0x1000
 ; CHECK-X86-64-NEXT:    movq $0, (%rsp)
@@ -14,6 +16,7 @@
 ; CHECK-X86-64-NEXT:    jne .LBB0_1
 ; CHECK-X86-64-NEXT:  # %bb.2:
 ; CHECK-X86-64-NEXT:    subq $2248, %rsp # imm = 0x8C8
+; CHECK-X86-64-NEXT:    .cfi_def_cfa_register %rsp
 ; CHECK-X86-64-NEXT:    .cfi_def_cfa_offset 71888
 ; CHECK-X86-64-NEXT:    movl $1, 264(%rsp)
 ; CHECK-X86-64-NEXT:    movl $1, 28664(%rsp)