diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -5069,6 +5069,13 @@
 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm",
            (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p,
                     cc_out:$s)>;
+// Alias for RSB with the ".w" optional width specifier, and with explicit
+// destination register.
+def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $Rm",
+           (t2RSBrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $ShiftedRm",
+           (t2RSBrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p,
+                    cc_out:$s)>;
 
 // SSAT/USAT optional shift operand.
 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s
--- a/llvm/test/MC/ARM/basic-thumb2-instructions.s
+++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s
@@ -2271,13 +2271,23 @@
 @------------------------------------------------------------------------------
         rsb r4, r8
         rsb r4, r9, r8
+        rsb.w r4, r9, r8
         rsb r1, r4, r8, asr #3
+        rsb.w r1, r4, r8, asr #3
         rsbs r2, r1, r7, lsl #1
+        rsbs.w r2, r1, r7, lsl #1
+        rsbs r0, r1, r2
+        rsbs.w r0, r1, r2
 
 @ CHECK: rsb	r4, r4, r8              @ encoding: [0xc4,0xeb,0x08,0x04]
 @ CHECK: rsb	r4, r9, r8              @ encoding: [0xc9,0xeb,0x08,0x04]
+@ CHECK: rsb	r4, r9, r8              @ encoding: [0xc9,0xeb,0x08,0x04]
+@ CHECK: rsb	r1, r4, r8, asr #3      @ encoding: [0xc4,0xeb,0xe8,0x01]
 @ CHECK: rsb	r1, r4, r8, asr #3      @ encoding: [0xc4,0xeb,0xe8,0x01]
 @ CHECK: rsbs	r2, r1, r7, lsl #1      @ encoding: [0xd1,0xeb,0x47,0x02]
+@ CHECK: rsbs	r2, r1, r7, lsl #1      @ encoding: [0xd1,0xeb,0x47,0x02]
+@ CHECK: rsbs	r0, r1, r2              @ encoding: [0xd1,0xeb,0x02,0x00]
+@ CHECK: rsbs	r0, r1, r2              @ encoding: [0xd1,0xeb,0x02,0x00]
 
 
 @------------------------------------------------------------------------------