diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9670,6 +9670,10 @@ unsigned NumUndefLanes = 0; SDValue Value; SDValue ConstantValue; + auto IsIntOrFPConstant = [](SDValue V) { + return isa(V) || isa(V); + }; + for (unsigned i = 0; i < NumElts; ++i) { SDValue V = Op.getOperand(i); if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) @@ -9680,10 +9684,10 @@ } if (i > 0) isOnlyLowElement = false; - if (!isa(V) && !isa(V)) + if (!IsIntOrFPConstant(V)) isConstant = false; - if (isa(V) || isa(V)) { + if (IsIntOrFPConstant(V)) { ++NumConstantLanes; if (!ConstantValue.getNode()) ConstantValue = V; @@ -9708,7 +9712,7 @@ // Convert BUILD_VECTOR where all elements but the lowest are undef into // SCALAR_TO_VECTOR, except for when we have a single-element constant vector // as SimplifyDemandedBits will just turn that back into BUILD_VECTOR. - if (isOnlyLowElement && !(NumElts == 1 && isa(Value))) { + if (isOnlyLowElement && !(NumElts == 1 && IsIntOrFPConstant(Value))) { LLVM_DEBUG(dbgs() << "LowerBUILD_VECTOR: only low element used, creating 1 " "SCALAR_TO_VECTOR node\n"); return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); diff --git a/llvm/test/CodeGen/AArch64/arm64-build-vector.ll b/llvm/test/CodeGen/AArch64/arm64-build-vector.ll --- a/llvm/test/CodeGen/AArch64/arm64-build-vector.ll +++ b/llvm/test/CodeGen/AArch64/arm64-build-vector.ll @@ -88,3 +88,20 @@ %add = fadd <1 x double> %arg, ret <1 x double> %add } + +; Make sure BUILD_VECTOR does not get stuck in a loop trying to convert a +; single element FP vector constant from a scalar to vector. +define <1 x double> @convert_single_fp_vector_constant(<1 x double>* %ptr, i1 %cmp) { +; CHECK-LABEL: convert_single_fp_vector_constant: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: tst w1, #0x1 +; CHECK-NEXT: mov x8, #4607182418800017408 +; CHECK-NEXT: csetm x9, ne +; CHECK-NEXT: fmov d0, x8 +; CHECK-NEXT: fmov d1, x9 +; CHECK-NEXT: and.8b v0, v0, v1 +; CHECK-NEXT: ret +entry: + %sel = select i1 %cmp, <1 x double> , <1 x double> zeroinitializer + ret <1 x double> %sel +}