diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -17,5 +17,9 @@ #include "clang/Basic/riscv_vector_builtins.inc" +// Zbb extension +TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb") +TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb") + #undef BUILTIN #undef TARGET_BUILTIN diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -11182,7 +11182,7 @@ "calling %0 is a violation of trusted computing base '%1'">, InGroup>; -// RISC-V V-extension -def err_riscvv_builtin_requires_v : Error< - "builtin requires 'V' extension support to be enabled">; +// RISC-V builtin required extension warning +def err_riscv_builtin_requires_extension : Error< + "builtin requires %0 extension support to be enabled">; } // end of sema component. diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -17882,6 +17882,17 @@ llvm::SmallVector IntrinsicTypes; switch (BuiltinID) { #include "clang/Basic/riscv_vector_builtin_cg.inc" + + // Zbb + case RISCV::BI__builtin_riscv_orc_b_32: + case RISCV::BI__builtin_riscv_orc_b_64: + ID = Intrinsic::riscv_orc_b; + IntrinsicTypes = {ResultType}; + break; + default: { + llvm_unreachable("unexpected builtin ID"); + return nullptr; + } // default } assert(ID != Intrinsic::not_intrinsic); diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -3415,13 +3415,29 @@ CallExpr *TheCall) { // CodeGenFunction can also detect this, but this gives a better error // message. + bool Feature_Missing = false; + SmallVector ReqFeatures; StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID); - if (Features.find("experimental-v") != StringRef::npos && - !TI.hasFeature("experimental-v")) - return Diag(TheCall->getBeginLoc(), diag::err_riscvv_builtin_requires_v) - << TheCall->getSourceRange(); + Features.split(ReqFeatures, ','); - return false; + // Check if each required feature is included + for (auto &I : ReqFeatures) { + if (TI.hasFeature(I)) + continue; + else { + // Make message like "experimental-zbr" to "Zbr" + I.consume_front("experimental-"); + std::string FeatureStr = I.str(); + FeatureStr[0] = std::toupper(FeatureStr[0]); + + // Error message + Feature_Missing = true; + Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension) + << TheCall->getSourceRange() << StringRef(FeatureStr); + } + } + + return Feature_Missing; } bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c @@ -0,0 +1,15 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix=RV32ZBB + +// RV32ZBB-LABEL: @orcb( +// RV32ZBB-NEXT: entry: +// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]]) +// RV32ZBB-NEXT: ret i32 [[TMP1]] +// +int orcb(int a) { + return __builtin_riscv_orc_b_32(a); +} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -0,0 +1,27 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbb -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix=RV64ZBB + +// RV64ZBB-LABEL: @orcb32( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV64ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]]) +// RV64ZBB-NEXT: ret i32 [[TMP1]] +// +int orcb32(int a) { + return __builtin_riscv_orc_b_32(a); +} + +// RV64ZBB-LABEL: @orcb64_2( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBB-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]]) +// RV64ZBB-NEXT: ret i64 [[TMP1]] +// +long orcb64_2(long a) { + return __builtin_riscv_orc_b_64(a); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -10,6 +10,21 @@ // //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// RISC-V Bitmanip (Bit Manipulation) Extension +// Zbb extension part + +let TargetPrefix = "riscv" in { + + class BitMan_GPR_Intrinsics + : Intrinsic<[llvm_any_ty], + [LLVMMatchType<0>], + [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; + + def int_riscv_orc_b : BitMan_GPR_Intrinsics; + +} // TargetPrefix = "riscv" + //===----------------------------------------------------------------------===// // Atomics diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -198,6 +198,9 @@ setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); } + if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit()) + setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom); + if (Subtarget.is64Bit()) { setOperationAction(ISD::ADD, MVT::i32, Custom); setOperationAction(ISD::SUB, MVT::i32, Custom); @@ -4168,6 +4171,14 @@ default: llvm_unreachable( "Don't know how to custom type legalize this intrinsic!"); + case Intrinsic::riscv_orc_b: { + SDValue Newop1 = + DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); + SDValue Res = + DAG.getNode(N->getOpcode(), DL, MVT::i64, N->getOperand(0), Newop1); + Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res)); + return; + } case Intrinsic::riscv_vmv_x_s: { EVT VT = N->getValueType(0); MVT XLenVT = Subtarget.getXLenVT(); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -831,6 +831,8 @@ /// Generic pattern classes +class PatGpr + : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>; class PatGprGpr : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>; class PatGprSimm12 diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -897,3 +897,7 @@ (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))), (PACKUW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbp, IsRV64] + +let Predicates = [HasStdExtZbb] in { +def : PatGpr; +} // Predicates = [HasStdExtZbb] diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll @@ -0,0 +1,21 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV32IB +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV32IBB + +declare i32 @llvm.riscv.orc.b.i32(i32) + +define i32 @orcb(i32 %a) nounwind { +; RV32IB-LABEL: orcb: +; RV32IB: # %bb.0: +; RV32IB-NEXT: orc.b a0, a0 +; RV32IB-NEXT: ret +; +; RV32IBB-LABEL: orcb: +; RV32IBB: # %bb.0: +; RV32IBB-NEXT: orc.b a0, a0 +; RV32IBB-NEXT: ret + %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) + ret i32 %tmp +} diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll @@ -0,0 +1,37 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV64IB +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV64IBB + +declare i32 @llvm.riscv.orc.b.i32(i32) + +define i32 @orcb32(i32 %a) nounwind { +; RV64IB-LABEL: orcb32: +; RV64IB: # %bb.0: +; RV64IB-NEXT: orc.b a0, a0 +; RV64IB-NEXT: ret +; +; RV64IBB-LABEL: orcb32: +; RV64IBB: # %bb.0: +; RV64IBB-NEXT: orc.b a0, a0 +; RV64IBB-NEXT: ret + %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) + ret i32 %tmp +} + +declare i64 @llvm.riscv.orc.b.i64(i64) + +define i64 @orcb64(i64 %a) nounwind { +; RV64IB-LABEL: orcb64: +; RV64IB: # %bb.0: +; RV64IB-NEXT: orc.b a0, a0 +; RV64IB-NEXT: ret +; +; RV64IBB-LABEL: orcb64: +; RV64IBB: # %bb.0: +; RV64IBB-NEXT: orc.b a0, a0 +; RV64IBB-NEXT: ret + %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a) + ret i64 %tmp +}