diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -17,5 +17,8 @@ #include "clang/Basic/riscv_vector_builtins.inc" +// Zbb extension +TARGET_BUILTIN(__builtin_riscv_orc_b, "LiLi", "nc", "experimental-zbb") + #undef BUILTIN #undef TARGET_BUILTIN diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -11167,7 +11167,7 @@ "calling %0 is a violation of trusted computing base '%1'">, InGroup>; -// RISC-V V-extension -def err_riscvv_builtin_requires_v : Error< - "builtin requires 'V' extension support to be enabled">; +// RISC-V builtin required extension warning +def err_riscv_builtin_requires_extension : Error< + "builtin requires %0 extension support to be enabled">; } // end of sema component. diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -17870,6 +17870,16 @@ llvm::SmallVector IntrinsicTypes; switch (BuiltinID) { #include "clang/Basic/riscv_vector_builtin_cg.inc" + + // Zbb + case RISCV::BI__builtin_riscv_orc_b: + ID = Intrinsic::riscv_orc_b; + IntrinsicTypes = {ResultType, Ops[0]->getType()}; + break; + default: { + llvm_unreachable("unexpected builtin ID"); + return nullptr; + } // default } assert(ID != Intrinsic::not_intrinsic); diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c @@ -0,0 +1,15 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix=RV32ZBB + +// RV32ZBB-LABEL: @orcb( +// RV32ZBB-NEXT: entry: +// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV32ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4 +// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 +// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32.i32(i32 [[TMP0]]) +// RV32ZBB-NEXT: ret i32 [[TMP1]] +// +long orcb(long a) { + return __builtin_riscv_orc_b(a); +} diff --git a/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -0,0 +1,15 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbb -emit-llvm %s -o - \ +// RUN: | FileCheck %s -check-prefix=RV64ZBB + +// RV64ZBB-LABEL: @orcb( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 +// RV64ZBB-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64.i64(i64 [[TMP0]]) +// RV64ZBB-NEXT: ret i64 [[TMP1]] +// +long orcb(long a) { + return __builtin_riscv_orc_b(a); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -10,6 +10,20 @@ // //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// RISC-V Bitmanip (Bit Manipulation) Extension +// Zbb extension part + +let TargetPrefix = "riscv" in { + + class BitMan_GPR_Intrinsics + : Intrinsic<[llvm_any_ty], [llvm_any_ty], + [IntrNoMem, IntrSpeculatable, IntrWillReturn]>; + + def int_riscv_orc_b : BitMan_GPR_Intrinsics; + +} // TargetPrefix = "riscv" + //===----------------------------------------------------------------------===// // Atomics diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -825,6 +825,8 @@ /// Generic pattern classes +class PatGpr + : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>; class PatGprGpr : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>; class PatGprSimm12 diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -874,3 +874,7 @@ (SRLIWPat GPR:$rs1, (i64 16)))), (PACKUW GPR:$rs1, GPR:$rs2)>; } // Predicates = [HasStdExtZbp, IsRV64] + +let Predicates = [HasStdExtZbb] in { +def : PatGpr; +} // Predicates = [HasStdExtZbb] diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll @@ -0,0 +1,21 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV32IB +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV32IBB + +declare i32 @llvm.riscv.orc.b.i32(i32) + +define i32 @orcb(i32 %a) nounwind { +; RV32IB-LABEL: orcb: +; RV32IB: # %bb.0: +; RV32IB-NEXT: orc.b a0, a0 +; RV32IB-NEXT: ret +; +; RV32IBB-LABEL: orcb: +; RV32IBB: # %bb.0: +; RV32IBB-NEXT: orc.b a0, a0 +; RV32IBB-NEXT: ret + %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) + ret i32 %tmp +} diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll @@ -0,0 +1,21 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV64IB +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=RV64IBB + +declare i64 @llvm.riscv.orc.b.i64(i64) + +define i64 @orcb(i64 %a) nounwind { +; RV64IB-LABEL: orcb: +; RV64IB: # %bb.0: +; RV64IB-NEXT: orc.b a0, a0 +; RV64IB-NEXT: ret +; +; RV64IBB-LABEL: orcb: +; RV64IBB: # %bb.0: +; RV64IBB-NEXT: orc.b a0, a0 +; RV64IBB-NEXT: ret + %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a) + ret i64 %tmp +}